International Business Machines Corporation

Globalfoundries Inc.

Cadence Design Systems, Inc.

Steven Michael Douskey

Michael John Hamilton

Amanda Renee Kaufer

Mary Prilotski Kusko

Ryan Andrew Fitch

Rudolf Adriaan Haring

Raghu Gaurav GopalaKrishnaSetty

Phillip A Senum

Steven Frederick Oakland

Paul Gregory Crumley

Arthur A Bright

Scott A Strissel

Marc B Dombrowa

Matthew B Schallhorn

Michael Richard Ouellette

William Vincent Huott

Paul Allen Ganfield

Frank William Angelotti

Hari Krishnan Rajeev

Brandon Edward Schenck

Frank David Ferraiolo

Cedric Lichtenau

James Douglas Warnock

Ronald Edward Fuhs

Leland Leslie Day

Guy Richard Currier

James Maurice Wallin

Daniel Mark Dreps

Franco Motika

Michael Stephen Floyd

John Michael Borkenhagen

Martin Ohmacht

Thomas Pflueger

Robert J Reese

Timothy Michael Skergan

Krishnan Sugavanam

Gerard M Salem

Robert Russell Williams

Paul William Rudrud

Orazio Pasquale Forlenza

Brion L Keller

Curtis Walter Preuss

Cédric Lichtenau

Matthew Roger Ellavsky

Dietmar Schmunkamp

Daniel Guy Young

Bruce George Rudolph

Ralph E Bellofatto

Wayne Allan Britson

Dennis Martin Rickert

Paul L Wiltgen

John Robert Elliott

Michael Allen Weed

Michael Richard Quellette

Moyra Kathleen McManus

Edward Michael Seymour

Sharon Denos Vincent

Paul W Wong

James Fred Daily

Jerome Martin Meyer

Kerry T Kaliszewski

Bryan J Weatherford

Raghu G Gaurav

Leah Marie Pfeifer Pastel

Sumit Panigrahi

James Donald Ryan

Michael Charles Cogswell

A method includes executing a test against a first structure and a second structure of a built-in self-test circuit. Each of the first and second structures include a plurality of latches arranged as a plurality of stump chains. The method also includes unloading a first result of the test from the plurality of stump chains of the first structure and a second result of the test from the plurality of stump chains of the second structure. The method further includes determining that the plurality of stump chains of the first structure includes a faulty latch based on the first result not matching the second result.

Diagnostic enhancement for multiple instances of identical structures

Operating pulsed latches on a variable power supply including turning on a first power rail powering a first latch of an integrated circuit, wherein the first latch is a pulsed latch; turning on a second power rail powering a second latch of the integrated circuit, wherein the second latch is operatively coupled to the first latch; performing a scan operation using the first latch and the second latch; turning off the first power rail powering the first latch; and performing a functional operation using the second latch, wherein the first power rail powering the first latch is off during the functional operation.

Operating pulsed latches on a variable power supply

Method and apparatus to test an integrated circuit includes retrieving power distribution data relating to an integrated circuit and designating a segment that includes at least one component of the integrated circuit. A switching limit associated with the segment may be set based on the power distribution data. Processes further generate a testing pattern that includes the determined switching limit associated with the segment.

Dynamically power noise adaptive automatic test pattern generation

A method and circuit are provided for implementing enhanced scan data testing with minimization of over masking in an on product multiple input signature register (OPMISR) test due to Channel Mask Enable (CME) sharing, and a design structure on which the subject circuit resides. A common Channel Mask Scan Registers (CMSR) logic is used with a multiple input signature register (MISR). Individual local addressing is used for implementing enhanced scan data testing. An architecture and algorithm efficiently expand and target the use of the CME pins to minimize over-masking, to increase test pattern effectiveness with the use of individual local addressing.

Minimization of over-masking in an on product multiple input signature register (OPMISR)

A method and circuit for implementing enhanced diagnostics with intelligent pattern combination in automatic test pattern generation (ATPG), and a design structure on which the subject circuit resides are provided. A random fault is selected in the design. A test pattern is generated and applied the test pattern to a design under test to test the selected random fault. The test is re-simulated to determine faults that are covered by the applied test pattern. A next iteration of test pattern generation includes selecting a fault that is based upon the previous test pattern generation for generating new test patterns.

Implementing enhanced diagnostics with intelligent pattern combination in automatic test pattern generation (ATPG)

A method and test circuit are provided for implementing enhanced scan data testing with minimization of over masking in an on product multiple input signature register (OPMISR) test, and a design structure on which the subject circuit resides. Common Channel Mask Scan Registers (CMSR) data is used with a multiple input signature register (MISR) in each satellite. A test algorithm control is used for implementing enhanced scan data testing by independently skewing scan unload shifting of selected OPMISR+ satellite by selected cycles. With this modified shifting, for the same test or a repeated run of the test, Channel Mask Enable (CME) triggered masking lines up on a different bit position in channels of each satellite avoiding over masking.

A method and test circuit are provided for implementing enhanced scan data testing with removal of over masking in an on product multiple input signature register (OPMISR) test, and a design structure on which the subject circuit resides. Common Channel Mask Scan Registers (CMSR) data is used with a multiple input signature register (MISR) in each satellite. A test algorithm control is used for implementing enhanced scan data testing to allow sharing the CMSR data and common Channel Mask Enable (CME) pins with removal of over masking. Selectively pausing scan unload is provided for each respective satellite when wrong CME data for the respective satellite is at the CME pins. Each satellite includes a select signal which controls advancing the scan into the MISR. The select signal is used to selectively pause the scan unload for the respective satellite.

Removal of over-masking in an on product multiple input signature register (OPMISR) test

A method and circuit for implementing enhanced scan data testing with decreased scan data interdependence for compressed patterns in on product multiple input signature register (OPMISR) testing through scan skewing, and a design structure on which the subject circuit resides are provided. The circuit is divided into multiple chiplets. Each chiplet includes a stump mux structure including multiple stump muxes connected in series, and a respective chiplet select is provided on shared scan inputs to respective chiplets. The chiplet select gates scan clocks, and when a chiplet is not selected the chiplet retains its data. The chiplet select enables test data to be skewed as scan data enters each chiplet.

Implementing decreased scan data interdependence for compressed patterns in on product multiple input signature register (OPMISR) through scan skewing

A method and circuit are provided for implementing enhanced scan data testing with over masking removal in an on product multiple input signature register plus (OPMISR+) test due to common Channel Mask Scan Registers (CMSRs) loading, and a design structure on which the subject circuit resides. An OPMISR plus satellite includes a multiple input signature register (MISR) for data collection and a plurality of associated scan channels. A common Channel Mask Scan Registers (CMSR) logic is used with the multiple input signature register (MISR). Unique CMSR data is loaded into at least one OPMISR plus satellite for implementing enhanced scan data testing. Scan pausing is used to reduce the amount of CMSR scan load data by loading the unique CMSR data only when needed.

Implementing over-masking removal in an on product multiple input signature register (OPMISR) test due to common channel mask scan registers (CMSR) loading

A method and circuit for implementing register array repair using Logic Built In Self Test (LBIST), and a design structure on which the subject circuit resides are provided. Register array repair includes identifying and creating a list of any repairable Register Arrays (RAs) that effect an LBIST fail result. Next a repair solution is detected for each of the repairable Register Arrays (RAs) isolating a failing location for the detected repair solution for each array.

Implementing register array (RA) repair using LBIST

Embodiments include methods, and processing system, and computer program products providing portion isolation design to a chip design to facilitate partial-good portion isolation test of the chip. Aspects include: retrieving a chip design file of a chip, the chip design file having pin related information from a chip design database, generating, via a pin group utility module, a pin group file according to the pin related information retrieved, combining, via a portion wrapper insertion utility module, the pin group file with one or more portion netlists to form one or more localized portion wrapper segments, stitching, via the portion wrapper insertion utility module, the one or more localized portion wrapper segments to form a portion boundary wrapper chain, and inserting, via the portion wrapper insertion utility module, the portion boundary wrapper chain into the chip design file to facilitate partial-good portion isolation test.

Portion isolation architecture for chip isolation test

Embodiments herein describe the design of a scan cell within an integrated circuit. The scan cell comprises a memory element, e.g., a flip-flop, and a plurality of output buffer stages. The scan cell also comprises selection logic, e.g., a plurality of transistors. The selection logic selectively activates and deactivates one or more of the plurality of output buffer stages in response to a scan enable signal to change an output latency of the scan cell. The scan cell operates in either a test mode or a normal functional mode according to the scan enable signal. The output latency of the scan cell is changed to mitigate or prevent hold violations.

Adjusting latency in a scan cell

A method and circuits are provided for implementing enhanced scan data testing using an XOR network to prioritize faults to be simulated during diagnostic isolation, and reducing the number of faults requiring re-simulation. A test is run, scan data are applied to scan channels using the XOR network and the output scan data are unloaded. A list of possible faults is identified based on pin flips, and the possible faults to be simulated during diagnostic isolation are prioritized by a number of occurrences in the list, and possible faults are further graded to reduce the number of possible faults requiring re-simulation.

Implementing prioritized compressed failure defects for efficient scan diagnostics

A method and system of testing an integrated circuit (IC), using a multiple input shift register (MISR) with supporting hardware for diagnosing failure locations in an IC with built-in self-test (BIST) logic, including an On-Product MISR. The system includes BIST logic of a circuit under test (CUT) and a tester including an isolation hash table (IHT) that translates signature fail data of the MISR to a failure location of a latch in the CUT. Signature fail data, and consequently, failure locations in the CUT, are obtained by standard testing of the CUT, testing of selected single channels of the CUT, and data insertion functions to the selected single channels of the CUT to obtain compressed MISR signature changes that, when translated, provide failure locations in the CUT.

Diagnosing failure locations of an integrated circuit with logic built-in self-test

Growing community of inventors

Rochester, MN, United States of America

Steven Michael Douskey