Infineon Technologies Ag

Steven Michael Baker

Michael Maldei

Guenter Gerstmeier

Jon Stanley Berry, Ii

Brian Cousineau

George William Alexander

Jinhwan Lee

David SuitWai Ma

Jennifer Faye Huckaby

Malati Hedge

Malati Hegde

Jinwhan Lee

Wenchao Zheng

Methods and apparatuses for adjusting trim settings for internally generated voltages of an integrated circuit device are provided. In one embodiment the apparatus receives a target digital value for an internally generated voltage, and compares the target digital value to a current digital value for the internally generated voltage. If the comparison indicates that a difference between the target digital value and the current digital value is greater than an allowable threshold, a trim setting used to trim the internally generated voltage is adjusted based on the difference. The trim setting may be adjusted until the difference between the target digital value and the current digital value is less than or equal to the allowable threshold.

Implementation of a fusing scheme to allow internal voltage trimming

A dynamic random access memory (DRAM) structure having a distance less than 0.14 um between the contacts to silicon and the gate conductor is disclosed. In addition a method for forming the structure is disclosed, which includes forming the DRAM array contacts and the contacts to silicon simultaneously.

High density DRAM with reduced peripheral device area and method of manufacture

A process for fabricating a semiconductor structure, wherein the semiconductor structure includes a core region and a periphery region. The core region includes a plurality of transistors and the periphery region includes a plurality of transistors. The process includes depositing a middle-of-line liner using plasma enhanced chemical vapor deposition overlying the semiconductor structure. By using a plasma enhanced chemical vapor deposition the amount of MOL liner deposited in the core region and the periphery region can be controlled depending on the distances between transistors in the core region and periphery region.

Maskless middle-of-line liner deposition

A dynamic random access memory (DRAM) structure having a distance less than 0.14 &#x3bc;m between the contacts to silicon and the gate conductor is disclosed. In addition a method for forming the structure is disclosed, which includes forming the DRAM array contacts and the contacts to silicon simultaneously.

A capacitor for a semiconductor device and a method of manufacturing a capacitor for a semiconductor device is disclosed that uses radial current flow. The capacitor includes a semiconductor substrate that includes a plurality of insulation islands. An insulation layer is formed over the semiconductor substrate. Gate electrodes are formed on top of the insulation layer. An array of CD contact pads including a plurality of CD contacts are connected to the semiconductor substrate in a first predetermined number of locations. An array of CG contact pads including at least one CG contact connected to the gate electrodes such that each CG contact is connected to a respective gate electrode above a respective insulation island in a second predetermined number of locations.

Microelectronic capacitor structure with radial current flow

A system and method for monitoring internal voltage sources in an integrated circuit, such as a DRAM integrated circuit, includes an internal analog multiplexing circuit, an internal analog-to-digital converter, and an interface circuit. Through the analog multiplexing circuit, the analog-to-digital converter sequentially connects to each voltage source and converts the measured voltage level of the source to a binary word. The interface circuit presents the binary word, e.g., serially, to test equipment off the integrated circuit.

System and method for monitoring internal voltages on an integrated circuit

A method of regulating a voltage of an internal voltage generator of an integrated circuit that includes sensing a temperature of an integrated circuit, comparing the sensed temperature with a voltage of a network of the integrated circuit and regulating a voltage of an internal voltage generator of the integrated circuit based on the comparing.

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Morrisville, NC, United States of America

Steven Michael Baker