International Business Machines Corporation

Cadence Design Systems, Inc.

Integrated Device Technology, Inc.

Steven Martin Broome

Loren Blair Reiss

Scott David Huss

Jason Alan Thurston

Fred Staples Stivers

Various embodiments provide for testing a transmitter with interpolation, which can be used with a circuit for data communications, such as serializer/deserializer (SerDes) communications. In particular, some embodiments provide for data transmission test of a transmitter by: generating and outputting a pre-determined data pattern through a serializer of the transmitter; sampling a serialized data output of the serializer over a plurality of different interpolation phase positions of a phase interpolator; and using a pattern checker to error check the sampled data over the plurality of different interpolation phase positions to determine whether the data transmission test passes.

Transmitter test with interpolation

An integrated circuitis provided with a clamp transistorfor providing electrostatic discharge event protection. A detector circuitproduces a clamp control signal for switching the clamp transistorto a conductive state so as to provide the electrostatic discharge protection. The detector circuitalso generates an electrostatic discharge event signalwhich is distributed elsewhere within the integrated circuitand controls a protection circuit elementto force a processing control signalof a signal processing transistorinto a state in which the signal processing transistoris more resistant to electrostatic discharge damage. The signal processing transistorsmay be P-type field effect transistors associated with a receiveror a transmitterconnected to an external signal communication line. The use of this active protection controlled by the electrostatic discharge event signalpermits smaller protection diodesto be use with such communication signal lines and/or provide for increased electrostatic discharge protection.

Electrostatic discharge event protection for an integrated circuit

A circuit and method provide a high valued resistance that is ideally used in low bandwidth filter and other signal processing applications. In one embodiment, an active device circuit includes first and second transistors, each having a gate, a source and a drain. The source voltages of the transistors change in response to an input signal voltage on an input terminal, and a current source constrains the gate to source voltages across the first and second transistors thus producing an output signal at an output terminal connected to the gate of the second transistor having a desired output resistance value based on the resistance across the drain and source terminals of the second transistor.

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Apex, NC, United States of America

Steven Martin Broome