International Business Machines Corporation

Steven Mark Thurber

Renato John Recio

Danny Marvin Neal

Douglas Morgan Freimuth

Richard Allen Kelley

William Gavin Holland

William Todd Boyd

Madeline Vega

Steven Wade Hunter

Gregory Michael Nordstrom

Claudia Andrea Salzberg

Richard Louis Arndt

Adalberto Guillermo Yanes

Gregory Francis Pfister

Aaron C Brown

Daniel Frank Moertl

Curtis Carl Wollbrink

Jacobo A Vargas

Guy L Guthrie

David R Engebretsen

Patrick Allen Buckland

William Joseph Armstrong

Richard Loise Arndt

Wen-Tzer Thomas Chen, Jr

Scott Neil Dunham

Giles R Frazier

Eric N Lais

Bruce Leroy Beukema

Edward John Silha

James O Nicholson

Bruce Gerard Mealey

Trung Ngoc Nguyen

James Anthony Pafumi

Bradly George Frey

Andrew Henry Wottreng

Carl Alfred Bender

Orvalle Theodore Kirby

George Henry Ahrens, Jr

Benjamin Herrenschmidt

John Thomas O'Quin, Ii

Kanisha Patel

Pat Allen Buckland

David Alan Bailey

Dono Van-Mierop

Thomas Anthony Gregg

Randal Craig Swanberg

Ronald Edward Fuhs

Mehul M Shah

Curtis Shannon Eide

John Ronald Oberly, Iii

Thomas Schlipf

Luke Matthew Browning

Scott Michael Willenborg

Douglas Craig Bossen

Travis James Pizel

Sean Thomas Brownlow

Charles Andrew McLaughlin

Ronald Ernest Freking

Timothy Joseph Torzewski

Joe C St Clair

James Arthur Lindeman

Ronald Stanley Wesely

Gary Yuh Tsao

Dan Marvin Neal

Amy M Youngs

Daniel F Moerti

Maneesh Sharma

Daniel Marvin Neal

Douglas M Fremiuth

Eric Norman Lais

In response to a determination to allocate additional storage, within a real address space employed by a system memory of a data processing system, for translation control entries (TCEs) that translate addresses from an input/output (I/O) address space to the real address space, a determination is made whether or not a first real address range contiguous with an existing TCE data structure is available for allocation. In response to determining that the first real address range is available for allocation, the first real address range is allocated for storage of TCEs, and a number of levels in the TCE data structure is retained. In response to determining that the first real address range is not available for allocation, a second real address range discontiguous with the existing TCE data structure is allocated for storage of the TCEs, and a number of levels in the TCE data structure is increased.

Configurable I/O address translation data structure

An apparatus and method for implementing multicast in system area network channel adapters are provided. With the apparatus and method, a multicast packet is received in a channel adapter of an end node. The channel adapter determines which local queue pairs are party of the multicast group identified by a destination local identifier in the multicast data packet. Based on this determination, the channel adapter replicates the data packet and delivers a copy of the data packet to each local queue pair that is part of the multicast group.

Implementing multicast on a system area network channel adapter

A mechanism is provided for sharing resources among logical partitions in a logical partitioned data processing system and for managing the changes to resources in such a way that the sharing operating systems are able to handle the various transitions in a graceful manner. Four hypervisor functions plus a specific return code manage the granting of access of resources owned by one partition to another (client) partition, accepting of granted resources by client partitions, returning of granted resources by client partitions, and rescinding of access by the owning partition. These four hypervisor functions are invoked either explicitly by the owning and client partitions or automatically by the hypervisor in response to partition termination. The hypervisor functions provide the needed infrastructure to manage the sharing of logical resources among partitions.

Managing the sharing of logical resources among separate partitions of a logically partitioned computer system

Mechanisms for communicating with a network adapter using a queue data structure are provided. A device driver invokes device driver services for initializing address translation and protection table (ATPT) entries in a root complex for the queue data structure. The device driver services return untranslated addresses to the device driver which are in turn provided to the network adapter. In response to retrieving a queue element from the queue data structure, the network adapter may request a translation of an untranslated address specified in the queue element and store the translated address in the network adapter prior to receiving a data packet targeting a buffer associated with the queue element.

Method for communicating with a network adapter using a queue data structure and cached address translations

An apparatus, program product and method dynamically bind Message Signaled Interrupt (MSI) resources shared by a plurality of clients to an interrupt facility in an MSI-capable computer. In addition, management of such bindings may be implemented using a platform independent interrupt manager capable of managing multiple MSI bindings between MSI resources to an interrupt facility, and interfaced with an underlying hardware platform of a computer through platform-specific encapsulation program code.

Message signaled interrupt management for a computer input/output fabric incorporating platform independent interrupt manager

In an embodiment, a north chip receives a secondary bus identifier that identifies a bus that is immediately downstream from a bridge in a south chip, a subordinate bus identifier that identifies a highest bus identifier of all of buses reachable downstream of the bridge, and an MMIO bus address range that comprises a memory base and a memory limit. The north chip writes a translation of a bridge identifier and a south chip identifier to the secondary bus identifier, the subordinate bus identifier, and the MMIO bus address range. The north chip sends the secondary bus identifier, the subordinate bus identifier, the memory base, and the memory limit to the bridge. The bridge stores the secondary bus identifier, the subordinate bus identifier, the memory base, and the memory limit in the bridge.

Memory mapped input/output bus address range translation

In an embodiment, a south chip comprises a first virtual bridge connected to a shared egress port and a second virtual bridge also connected to the shared egress port. The first virtual bridge receives a first secondary bus identifier, a first subordinate bus identifier, and a first MMIO bus address range from a first north chip. The second virtual bridge receives a second secondary bus identifier, a second subordinate bus identifier, and a second MMIO bus address range from a second north chip. The first virtual bridge stores the first secondary bus identifier, the first subordinate bus identifier, and the first MMIO bus address range. The second virtual bridge stores the second secondary bus identifier, the second subordinate bus identifier, and the second MMIO bus address range. The first north chip and the second north chip are connected to the south chip via respective first and second point-to-point connections.

Memory mapped input/output bus address range translation for virtual bridges

A mechanism for temporarily stalling selected Direct Memory Access (DMA) operations in a physical input/output (I/O) adapter in order to permit migration of data between physical pages that are subject to access by the physical I/O adapter. When a request for a DMA to a physical page in system memory is received from an I/O adapter, a migration in progress (MIP) bit in a translation control entry (TCE) pointing to the physical page is examined, wherein the MIP bit indicates whether migration of the physical page referenced in the TCE to another location in system memory is currently in progress. If the MIP bit indicates a migration of the physical page is in progress, the DMA from the I/O adapter is temporarily stalled while other DMA operations from other I/O adapters to other physical pages in system memory are allowed to continue.

Stalling of DMA operations in order to do memory migration using a migration in progress bit in the translation control entry mechanism

In an embodiment, a translation of a hierarchical bus number to a physical bus number and a bridge identifier of a bridge are written to a north chip. A request is received that comprises an identifier of a destination. A determination is made that the identifier comprises the hierarchical bus number. In response to the determination, the identifier of the destination is replaced in the request with the physical bus number and the bridge identifier. The request is sent to the bridge identified by the bridge identifier. A south chip comprises the bridge, and the south chip is connected to the north chip via a point-to-point serial link. The physical bus number identifies a bus that connects the bridge to a device. The request comprises a configuration write request that requests a write of data to the device.

Hierarchical to physical bus translation

A method, system and computer program product are provided for implementing PCI-Express memory domains for single root virtualized devices. A PCI host bridge (PHB) includes a memory mapped IO (MMIO) domain descriptor (MDD) and an MMIO Domain Table (MDT) are used to associate MMIO domains with PCI memory VF BAR spaces. One MDD is provided for each unique VF BAR space size per bus segment connecting a single root IO virtualization (SRIOV) device to the PCI host bridge (PHB). The MDT used with the MDD includes having a number of entries limited to a predefined total number of SRIOV VFs to be configured. A VF BAR Stride, which may be further implemented as a VF BAR Stride Capability Structure, is provided to reduce the number of MDDs required to map SRIOV VF BAR spaces. A particular definition of the MDD is provided to reduce the number of MDDs required to at most one per SRIOV bus segment below a PHB.

Implementing PCI-express memory domains for single root virtualized devices

A computer-implemented method may include determining that a slot coupled to a peripheral component interconnect host bridge is occupied by an input/output adapter. The computer-implemented method may include determining one or more characteristics of the input/output adapter and determining whether the input/output adapter is capable of using additional memory based on the one or more characteristics of the input/output adapter. The computer-implemented method may also include allocating the additional memory for the input/output adapter in response to determining that the input/output adapter is capable of using the additional memory.

Dynamic allocation of a direct memory address window

In an embodiment, a translation of a hierarchical MMIO address range to a physical MMIO address range and an identifier of a bridge in a south chip are written to a north chip. A transaction is received that comprises a hierarchical MMIO address. The hierarchical MMIO address that is within the hierarchical MMIO address range is replaced in the transaction with the identifier of the bridge and with a physical MMIO address that is within the physical MMIO address range in the south chip. The transaction is sent to the device that is connected to the bridge in the south chip. The physical MMIO address range specifies a range of physical MMIO addresses in memory in the device.

Hierarchical to physical memory mapped input/output translation

Mechanisms are provided for implementing a multi-root PCI manager (MR-PCIM) in a multi-root I/O virtualization management partition (MR-IMP) to control the shared functionality of an multi-root I/O virtualization (IOV) enabled switch fabric and multi-root IOV enabled I/O adapter (IOA) through the base functions (BF) of the switches and IOAs. A hypervisor provides device-independent facilities to the code running in the I/O Virtualization Management Partition (IMP), Multi-Root (MR)-IMP and client partitions. The MR-IMP may include device specific code without the hypervisor needing to sacrifice its size, robustness, and upgradeability. The hypervisor provides the virtual intermediary functionally for the sharing and control of the switch and IOA's control functions.

Multi-root I/O virtualization using separate management facilities of multiple logical partitions

Growing community of inventors

Austin, TX, United States of America

Steven Mark Thurber