Lsi Logic Corporation

Lsi Corporation

Steven Mark Emerson

Gregory F Hammitt

Judy M Gehman

Jeffrey J Holm

John M Nystuen

Matthew D Kirkwood

Balraj Singh

Steven G Kopacek

Jonathan W Byrn

Gary Michael Lippert

Stefan G Auracher

Donald Gabrielson

Douglas J McKenney

A system comprising a plurality of controller circuits, a plurality of line buffer circuits and an arbiter. The plurality of control circuits may each be configured to store data. The plurality of line buffer circuits may each be configured to transfer data between an accessed one of the controller circuits and one of a plurality of first busses. The arbiter circuit may be configured to control access to the controller circuits by the line buffer circuits.

AMBA modular memory controller

A reusable software block is adapted to control multiple instantiations of a peripheral device within a system. A device hardware abstraction layer defines offset values for registers of the peripheral device and a data structure for the peripheral device. A platform hardware abstraction layer defines an address map of the system, and is adapted to initialize each instantiation of the peripheral device via calls to the device hardware abstraction layer.

System and method for implementing multiple instantiated configurable peripherals in a circuit design

A method and apparatus are provided for interfacing with a synchronous dynamic memory in which memory commands are provided to the memory. The memory is accessed in response to the memory commands. Read data is captured in a data capture circuit having a delay setting. The delay setting is updated in response to detection of a period of read inactivity of the memory.

Method and apparatus for self-adjusting input delay in DDR-based memory systems

A system for RTL test insertion in an integrated circuit layout pattern includes a core module, a test wrapper, and a smart wrapper. The core module describes a function defined by logical elements, interconnections between logical elements, input pins and output pins. The test wrapper is adapted to encapsulate the core module and to create test pins representing the core module. The smart wrapper is adapted to encapsulate the test wrapper and to assign the test pins to a non-asserted state. The smart wrapper is adapted to place an assertion on one or more of the test pins for static or dynamic testing of the integrated circuit layout pattern.

Method for abstraction of manufacturing test access and control ports to support automated RTL manufacturing test insertion flow for reusable modules

A method for designing and using a partially manufactured semiconductor product is disclosed. The partially manufactured semiconductor product, referred to as a slice, contains a fabric of configurable transistors and at least an area of embedded memory. The method contemplates that a range of processors, processing elements, processing circuits exists which might be manufactured as a hardmacs or configured from the transistor fabric of the slice. The method then evaluates all the memory requirements of all the processors in the range to create a memory superset to be embedded into the slice. The memory superset can then be mapped and routed to a particular memory for one of the processors within the range; ports can be mapped and routed to access the selected portions of the memory superset. If any memory is not used, then it and/or its adjoining transistor fabric can become a landing zone for other functions or registers or memories.

Flexible design for memory use in integrated circuits

A circuit comprising a plurality of first line buffers, an arbiter and a cache. The plurality of first line buffers may be configured to communicate on a plurality of first busses. The arbiter may be configured to perform an arbitration among the first line buffers. The cache block may be configured to (i) determine a particular policy of a plurality of policies in response to a first transaction request from one of the first line buffers winning the arbitration and (ii) generate a second transaction request based upon the first transaction request and the particular policy.

Ternary CAM with software programmable cache policies

A memory controller system is provided, which includes a plurality of system buses, a multi-port memory controller and a plurality of error correcting code (ECC) encoders. The memory controller has a plurality of system bus ports and a memory port. Each ECC encoder is coupled between a respective system bus and a respective system bus port of the memory controller.

Multi-port memory controller having independent ECC encoders

A circuit generally comprising a command buffer and a read buffer is disclosed. The command buffer may be configured to (i) buffer a plurality of read commands received by the circuit, wherein each read command has one of a plurality of port values and one of a plurality of identification values and (ii) transmit a tag signal from the circuit in response to servicing a particular read command of the read commands. The tag signal may have a particular port value of the port values and a particular identification value of the identification values as determined by the particular read command. The read buffer may be configured to transmit a read signal within a plurality of first transfers from the circuit in response to servicing the particular read command.

A communications module for a data communications system having a plurality of data processors comprises a plurality of ports, each coupled to a respective one of the data processors. An address table associates addresses of a memory space to addresses of the data processors. The memory space may include addressable FIFOs, SRAM memory and/or flag registers. In the case of FIFOs, a counter coupled to the FIFO supplies a flag or ready signal indicating the not-full or not-empty status of the respective FIFO, which is supplied to a master device that is writing data to the FIFO or that is reading data from the FIFO so that the writing master device will write only when the FIFO is not full and the reading master device will read only when the FIFO is not empty.

Multi-core communications module, data communications system incorporating a multi-core communications module, and data communications process

A method of operating a circuit is disclosed. The method generally comprises the steps of (A) generating a particular policy of a plurality of policies by a lookup operation on a first transaction request received by the circuit, (B) generating a second transaction request for use by a memory external to the circuit based upon the first transaction request and the particular policy in response to a first cache signal of the first transaction request having a non-cacheable state and (C) searching a plurality of address tags for cache data cached within the circuit for a match with the first transaction request in response to the first cache signal having a cacheable state.

Method for use of ternary CAM to implement software programmable cache policies

A method for resource notification is disclosed. The method generally comprises the steps of (A) buffering a plurality of messages received from a plurality of busses, (B) arbitrating among the messages, (C) writing the messages in response to the arbitration, and (D) generating a plurality of notification signals on a plurality of lines in response to the messages as written to a plurality of addresses.

System method for use of hardware semaphores for resource release notification wherein messages comprises read-modify-write operation and address

A data bus system transfers words and word portions on a data bus between master devices and slave devices. A size bus carries a size code in fixed-byte format that identifies a number of bytes being transferred in one or more words and/or word portions of a transaction. A byte-enable bus carries a byte-enable code that identifies valid bytes of a word. An interface decodes the byte-enable codes to size codes and, where an odd-byte byte-enable code is decoded, it decodes the odd-byte byte-enable code to a plurality of size codes.

Byte-enabled transfer for a data bus having fixed-byte data transfer

The present invention is directed to a system and method for heterogeneous multiprocessor reference design. In an aspect of the present invention, a method of designing a multiprocessor integrated circuit may include receiving a specification for an integrated circuit having multiprocessors, the specification having a desired functionality. Functional components are chosen which provide the desired functionality of the received specification. The functional components are implemented in a modular multiprocessor reference design as an example system for the multiprocessor integrated circuit. The implemented functional components of the modular multiprocessor reference design may be suitable for testing software for operation by the multiprocessor integrated circuit. Moreover, the modular multiprocessor reference design enables testing of interaction of functional components for providing the desired functionality of the received specification.

Heterogeneous multi-processor reference design

A bus bridge generally comprising a first interface, a second interface, a plurality of registers and a controller. The first interface may be connectable to a first bus having a first data width. The second interface may be connectable to a second bus having a second data width narrower than the first data width. The plurality of registers may be configured to buffer (i) data, (ii) an address, and (iii) a plurality of control signals between the first bus and the second bus. The controller configured to control the registers.

AHB segmentation bridge between busses having different native data widths

A system, such as an AMBA based system, wherein an interrupt controller is coupled directly to a processor, thereby providing that the processor can access the interrupt controller without having to access a system bus. Specifically, the interrupt controller may be coupled to a port of the processor, such as a tightly coupled memory (TCM) port or a coprocessor port of the processor. The interrupt controller may be coupled to the TCM port along with SRAM.

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Chanhassen, MN, United States of America

Steven Mark Emerson