Globalfoundries U.S. Inc.

International Business Machines Corporation

Globalfoundries Inc.

Globalfoundries U.S. 2 LLC

Elpis Technologies Inc.

Steven M Shank

Anthony K Stamper

John J Ellis-Monaghan

Siva P Adusumilli

Solomon Assefa

Vibhor Jain

Bruce Walter Porth

John Joseph Pekarik

Jeffrey P Gambino

Yusheng Bian

Marwan H Khater

Mark David Jaffe

James Spiros Nakos

Michel J Abou-Khalil

Uzma B Rana

Ajey Poovannummoottil Jacob

Qizhi Liu

Timothy Wayne Kemerer

Rajendran Krishnasamy

William M Green

Edward William Kiewra

Alvin Jose Joseph

Jay Sanford Burnham

Tymon Barwicz

Yurii A Vlasov

Michael Joseph Zierak

Mark Levy

Yves T Ngu

Ramsey M Hazbun

Jessie Carrigan Rosenberg

Ian McCallum-Cook

Michael C Triplett

James J Quinlivan

Mousa H Ishaq

Beth A Ward

Jenifer E Lary

Deborah A Tucker

Judson Robert Holt

Evgeni Petrovich Gousev

Jeffrey C Maling

Patrick Ronald Varekamp

Cameron E Luce

Douglas Andrew Buchanan

James Randall Elliott

Venkata N R Vanukuru

Dinh Dang

William M J Green

Aaron Vallett

Wade J Hodge

Carol J Heenan

June Cline

Zhong-Xiang He

Herbert Lei Ho

Robert Mark Rassel

Robert K Leidy

Jason Scott Orcutt

Richard A Phelps

Roderick Alan Augur

Kenneth John Giewont

Johnatan A Kantarovsky

Michal Rakowski

Francis Roger White

Russell T Herrin

Dale Warner Martin

Mickey H Yu

Leah M Pastel

Brett T Cucci

John Z Colt, Jr

Thai Doan

Swetha Kamlapurkar

Pernell Dongmo

Sarah A McTaggart

Laura J Schutz

Toshiharu Furukawa

Robert J Gauthier, Jr

Kirk David Peterson

Xuefeng Liu

Alain F Loiseau

James Albert Slinkman

Anthony I Chou

Shesh Mani Pandey

Eric Jeffrey White

William Joseph Murphy

Alan Bernard Botula

Theodore James Letavic

Bartlomiej Jan Pawlak

Karen A Nummy

Alexander M Derrickson

Jens Hofrichter

Nicholas A Polomoff

Ephrem G Gebreselasie

Gary L Milo

Casey Jon Grant

Michael J Hauser

Keith Donegan

Brennan J Brown

Heidi L Greer

Blaine Jeffrey Gross

Ahmed Y Ginawi

Margaret L Gibson

The present disclosure relates to semiconductor structures and, more particularly, to a bipolar transistor and methods of manufacture. The structure includes: a collector region; an extrinsic base comprising an emitter opening with an angled sidewall; an emitter within the emitter opening; and an intrinsic base between the emitter and the collector.

Bipolar transistor

The present disclosure relates to semiconductor structures and, more particularly, to field effect transistors and methods of manufacture. The structure includes: at least one gate structure comprising source/drain regions; and at least one isolation structure perpendicular to the at least one gate structure and within the source/drain regions.

Field effect transistor with shallow trench isolation features within source/drain regions

The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors (HBTs) with a buried trap rich isolation region and methods of manufacture. The structure includes: a first heterojunction bipolar transistor; a second heterojunction bipolar transistor; and a trap rich isolation region embedded within a substrate underneath both the first heterojunction bipolar transistor and the second heterojunction bipolar transistor.

Heterojunction bipolar transistor with buried trap rich isolation region

The present disclosure relates to semiconductor structures and, more particularly, to photodiodes and methods of manufacture. The structure includes: a top terminal; an intrinsic material in contact with the top terminal; and a bottom terminal in contact with the intrinsic material, the bottom terminal including a P semiconductor material and a fully depleted N semiconductor material.

Photodiodes

A structure includes a dielectric waveguide, and at least one grating coupler adjacent the dielectric waveguide. Each grating coupler includes a set of parallel optofluidic grating channels oriented orthogonally to the dielectric waveguide. The structure may also include a radiation source operatively coupled to the dielectric waveguide, and an optical receiver such as a photosensor adjacent the grating coupler(s). The structure may be used as part of an optofluidic sensor system for, for example, biochemical applications.

Structure including grating coupler with optofluidic grating channels

Structures including an electro-absorption modulator and methods of forming such structures. The structure comprises a waveguide core including a first tapered section, a second tapered section, and a longitudinal axis. The first tapered section and the second tapered section are aligned along the longitudinal axis. The structure further comprises a first waveguide taper overlapping the first tapered section of the waveguide core, a second waveguide taper overlapping the second tapered section of the waveguide core, and a multiple-layer structure on the waveguide core between the first waveguide taper and the second waveguide taper.

Electro-absorption modulators with stacked waveguide tapers

Structures for a transistor including regions for landing gate contacts and methods of forming a structure for a transistor that includes regions for landing gate contacts. The structure includes a field-effect transistor having a source region, a gate region, a gate with a sidewall, and a gate extension with a section adjoined to the sidewall. The structure further includes a dielectric layer over the field-effect transistor, and a gate contact positioned in the dielectric layer to land on at least the section of the gate extension.

Contact-over-active-gate transistor structures with contacts landed on enlarged gate portions

Semiconductor structures including electrical isolation and methods of forming a semiconductor structure including electrical isolation. The structure includes a semiconductor substrate having a first surface, a recess in the first surface, and a second surface inside the first recess. The structure further includes a shallow trench isolation region extending from the first surface into the semiconductor substrate. The shallow trench isolation region is positioned to surround an active device region including the recess. A field-effect transistor includes a gate electrode positioned on a portion of the second surface.

Field-effect transistors having a gate electrode positioned inside a substrate recess

The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors (HBTs) with a buried trap rich region and methods of manufacture. The structure includes: a trap rich isolation region embedded within the bulk substrate; and a heterojunction bipolar transistor above the trap rich isolation region, with its sub-collector region separated by the trap rich isolation region by a layer of the bulk substrate.

The present disclosure relates to semiconductor structures and, more particularly, to field effect transistors and methods of manufacture. The structure includes: at least one gate structure having source/drain regions; at least one isolation structure within the source/drain regions in a substrate material; and semiconductor material on a surface of the at least one isolation structure in the source/drain regions.

Field effect transistor

An integrated circuit (IC) structure, a switch and related method, are disclosed. The IC structure includes an active device, e.g., a switch, over a bulk semiconductor substrate, and an isolation structure under the active device in the bulk semiconductor substrate. The isolation structure may include a trench isolation adjacent the active device in the bulk semiconductor substrate, a dielectric layer laterally adjacent the trench isolation and over the active device, and a porous semiconductor layer in the bulk semiconductor substrate under the dielectric layer laterally adjacent the trench isolation. The IC structure employs a lower cost, low resistivity bulk semiconductor substrate rather than a semiconductor-on-insulator (SOI) substrate, yet it has better performance characteristics for RF switches than an SOI substrate.

IC structure including porous semiconductor layer in bulk substrate adjacent trench isolation

An integrated circuit (IC) structure includes an active device over a bulk semiconductor substrate, and an isolation structure around the active device in the bulk semiconductor substrate. The isolation structure includes: a polycrystalline isolation layer under the active device, a trench isolation adjacent the active device, and a porous semiconductor layer between the trench isolation and the bulk semiconductor substrate.

IC structure including porous semiconductor layer under trench isolation

The present disclosure relates to semiconductor structures and, more particularly, to photodetectors with buried airgap mirror reflectors. The structure includes a photodetector and at least one airgap in a substrate under the photodetector.

Photodetector with buried airgap reflectors

A structure includes a field effect transistor (FET) stack including a plurality of transistors over a buried insulator layer. A polysilicon isolation region is in a substrate below the FET stack and the buried insulator layer. A resistor network is in the polysilicon isolation region, the resistor network having a different resistivity than the polysilicon isolation region. The resistor network may include a resistive wire having a first width and a resistive pad within the resistive wire under each FET in the FET stack. Each resistive pad has a second width larger than the first width of the resistive wire. A length of the resistive wire is different aside each resistive pad to adjust a threshold voltage of an adjacent FET in the FET stack to a predetermined value to compensate for non-linear voltage distribution between an input and an output of the FET stack.

Structure including resistor network for back biasing FET stack

Disclosed are a structure with a substrate-embedded waveguide and a method of forming the structure. The waveguide includes cladding material lining a trench in a substrate, a core in the trench on the cladding material, and at least one cavity within the core. Each cavity extends from one end of the core toward the opposite end and contains a low refractive index material or is under vacuum so the waveguide is an arrow waveguide. An insulator layer is on the substrate and extends laterally over the waveguide and a semiconductor layer is on the insulator layer. Additionally, depending upon the embodiment, an additional waveguide can be aligned above the substrate-embedded waveguide either on the isolation region or on a waveguide extender that extends at least partially through the isolation region and the insulator layer to the waveguide.

Structure with substrate-embedded arrow waveguide and method

Growing community of inventors

Jericho, VT, United States of America

Steven M Shank