Apple Inc.

Oracle America, Inc.

Electric Editor, Inc.

Steven M Rubin

Robert E Mains

George J Chen

Gilda Garreton

Various methods and apparatus for executing a multithreaded algorithm that performs a static timing analysis of an integrated circuit chip (chip) include logic for traversing the chip to identify a plurality of components (cells or nodes) within a chip circuit of the chip. A waveform graph is defined for the identified nodes. One or more virtual graphs are generated from the waveform graph. The plurality of nodes in the one or more virtual graphs are processed using multiple threads to obtain quadruplet of time domain dataset values representing the different modes of propagation for each node. A timing check is performed at an end node of the virtual graphs using the quadruplet of time domain dataset values to determine any timing violation within the chip design.

Highly threaded static timer

A method for controlling a three dimensional cursor's position on a display with a two dimensional control device by generating a translation signal to the display when the control device was moved in such a way as to indicate that the user intended a translation of the cursor and generating an elevation signal to the display when the control device was moved in such a way as to indicate that the user intended an elevation of the cursor. Analysis of the single movement alone, however, being only the first step in truly interpreting the user's intentions, the present invention also includes steps for preventing certain types of control device movements from being interpreted incorrectly.

Three dimensional cursor

An electrical design system is described which integrates many analysis and synthesis tools in an environment of top-down circuit layout. The system allows electrical design in numerous technologies, including nMOS, CMOS, bipolar, printed circuit boards and others. Technologies and analysis or synthesis tools may be added or deleted easily, and different technologies may be employed in a single design. The system includes a database manager which maintains all information regarding the design of the circuit, and which is accessed by all of the analysis and synthesis tools to enable them to examine and modify the design. The database itself is structured as a network of electrically connected and geometrically described components. Each component in the database is considered a node, and connections among components are considered as arcs. Changes are permitted only to nodes, and constraints are imposed only upon arcs. When components are changed, the effects of the changes are propagated to surrounding components by the arcs. In this manner the database manager insures that the circuit remains properly connected throughout the design process while allowing the propagation of changes up and down the hierarchy.

Growing community of inventors

Portola Valley, CA, United States of America

Steven M Rubin