Unisys Corporation

Sperry Corporation

Steven M O'Brien

Michael J Saunders

Arthur J Nilson

James W Thompson

Frank J Leisz

Jeffrey A Stell

Dennis J Davidowski

Jayant S Pandya

A method and apparatus for ensuring the coherence of multiple copies of the same data at multiple geographic locations is presented. The system operating system, the system operator or some combination of both may determine the physical disks having the file or comprising the disk families containing data which requires protection. Using the MIRROR CREATE commands in a Unisys MCP operating system environment, a mirrored disk pack set is made for each relevant physical disk identified. The disk pack set is distributed amongst at least two geographic locations. For each member of each disk pack set, the STORESAFE&plus;command associates a site identifier with the member corresponding to the member's geographic location. During application processing, disk writes for one member of a mirrored set are performed for each member of the set. The MCP operating system checks the results of each disk write to each of the members of the mirrored disk set. If the MCP operating system determines that a write was successful for at least one member of the mirrored set at each geographic location, then a &ldquo;good&rdquo; I/O result is returned to the application and application processing continues normally. By contrast, if the MCP operating system determines that for least one site identifier, no member of the set assigned the identifier experienced a successful disk write, then an IOERROR is returned, and application processing may optionally be halted.

Method and apparatus for ensuring data integrity

A mainframe computing system is adapted to be loaded with one of a plurality of different operating systems and different associated microcode to provide a computing system which is capable of running user programs adapted to be executed by the loaded operated system comprises a main memory for receiving the desired operating system coupled to a system bus. An instruction processor and an input/output control processor are coupled to the system bus and are provided with an instruction register for presenting user program instructions to the processors. The processor means have associated therewith microcode storage memory which receive and store a set of microcode instructions to be performed by the processors according to the program instruction stored in the instruction register. The stored microcode comprises primary microcode instructions to carry out each of the instructions in the instruction register means. No compiling or emulation is necessary to provide a software configurable computing system adapted to run user programs according to one of a plurality of operating systems loadable in the main memory.

Dual operating system computer

An apparatus for enhancing the operation of a M byte instruction word CPU when operating user programs on an N byte instruction word CPU. The M-Byte instruction word CPU is provided with an N-Byte instruction register and a main memory for supplying N-Byte instruction words or M-Byte instruction words to said N-Byte instruction register. An operational code multiplexer and an parameter code multiplexer are connectable to selective outputs of said instruction register so that any one of the M-Bytes may be selected as an operational code and any one of the remaining M-Bytes may be selected as parameter code bytes, and selection means including sequencer means are provided for operating the operational code multiplexer and the parameter code multiplexer in an M-Byte instruction word CPU mode of operation or as an N-Byte instruction word CPU mode of operation.

N-byte stack-oriented CPU using a byte-selecting control for enhancing a

The present invention provides a novel programmable data communications controller employed to accept data from a host computing system and for transmitting the data to a terminal designated by the host computer system. The data computer communications controller is further provided with protocols, parameters and poll tables stored in a dedicated memory of the data communications controller which enables the controller to receive data and address information from a main memory of a host computer and to reformat and pre-package the information in a protocol format block acceptable by a terminal coupled to the data communications controller. Different protocols, parameters and polls are provided in the data communications controller in the form of preprogrammed information which enables different terminals employing different protocols and protocol formats to be coupled directly to a data link interface bus without hardware modifications. Different protocols are loaded into the main memory of the main computer system and down loaded into the bit map memory of the data communications controller upon initialization of the system.

Programmable data communications controller

In a high speed data processing system, there is provided a circuit for shifting either right or left as data is transmitted to or from the main storage unit. Apparatus for high speed parallel byte shifting is connected to the data bus which connects the main storage unit to the system and comprises logic which selects predetermined byte lines. Information from the individually selected byte lines is temporarily stored in parallel buffer registers and subsequently returned to a different byte line to provide byte shifting without the requirement of shift registers or complex logic.

High speed byte shifter for a bi-directional data bus

A switching circuit for automatically selecting one of a plurality of normally operable asynchronous oscillators is provided with a selection switch for selecting a new oscillator while the formerly selected oscillator is still producing an output. The switching circuit employs the output of the newly selected oscillator to disable the formerly selected oscillator and to subsequently enable the output of the newly selected oscillator to be coupled to the oscillator output of the switching circuit, thus, preventing switch-over from one oscillator to the other during a metastable period.

Automatic synchronous switch for a plurality of asynchronous oscillators

The present apparatus includes logic for stopping timing circuits in a central processing unit and for restarting the timing circuits to produce timing signals synchronized with an asynchronous external signal. The continuous running master clock of the central processing unit is employed to generate a plurality of phase related new clock signals. Logic circuit means are provided to sequentially attempt to employ each of the new clock signals until one of the new clock signals synchronizes with the external asynchronous signal. The logic circuit means include circuits for selecting a new clock signal to be employed by the timing circuits of the central processing unit so that the new clock is synchronized with the external asynchronous signal.

High speed processing restarting apparatus

Apparatus for checking the correct operation of a parallel byte shifter of the type having a plurality of input ports connected to individual byte lines of a data bus. When predetermined byte lines to the byte shifters are selected, control means are provided to activate a set of shift select means connected to error checking circuits. The error checking circuits comprise logic gating means for checking the proper selection of byte lines and for storing a signal indicative of an error or absence of an input error in the error storage means. When the data byte is being transferred out or read out of the byte shifter, the error storage means is read out to determine the presence or absence of an output error from the error storage means.

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Norristown, PA, United States of America

Steven M O'Brien