Micron Technology Incorporated

Other

Steven M McDonald

Warren M Farnworth

Mark E Jost

David J Hansen

Ravi T Iyer

Zhiping Yin

Dale Collins

Jeffrey W Honeycutt

Thomas R Glass

Salman Akram

William Mark Hiatt

Nishant Sinha

John R C Futrell

Kunal R Parekh

Werner Juengling

Substrate precursor structures include a substrate blank having at least one aperture extending substantially through the substrate blank. At least a portion of at least one conductive layer covers a surface of the at least one aperture of the substrate blank. A mask pattern covers a portion of the at least one conductive layer and exposes another portion of the at least one conductive layer to define at least one conductive element, at least a portion of which extends over the surface of the at least one aperture.

Methods of fabricating substrates including one or more conductive vias

A method of fabricating a substrate is disclosed. Apertures are formed in a substrate blank. A conductive layer is formed on opposing surfaces of the substrate, as well as inside the apertures. Conductive elements are defined on one or both opposing surfaces by masking and etching. Additional layers of conductive materials may be used to provide a barrier layer and a noble metal cap for the conductive elements. The methods of the present invention may be used to fabricate an interposer for use in packaging semiconductor devices or a test substrate. Substrate precursor structures are also disclosed.

Methods of fabricating substrates including at least one conductive via

Methods are provided for creating lined vias in semiconductor substrates. Using electrophoretic deposition techniques, micelles of a lining material are deposited on the wall of the via, reacting with the surface of the wall until the entire wall is covered by the lining material. The lining material is then fixed in place to form a layer lining the via. The lined via may then be filled with a desired material. For example, a via lined with an insulative material may be filled with a material such as copper to create an insulated conductive via through the substrate.

Semiconductor structures having electrophoretically insulated vias

The invention includes methods by which a fuse box of a semiconductor construction is fabricated to have a substantially uniform layer over fuses extending therein. In particular aspects, the invention includes methods in which one or more processing steps associated with fabrication and patterning of bond pads and redistribution layers is conducted simultaneously over a fuse box region to form and/or remove materials that are directly over the fuse box region.

Methods of forming semiconductor constructions

Methods for creating electrophoretically insulated vias in semiconductive substrates

A semiconductor component configured for wafer-level testing includes a semiconductor die having at least one die contact electrically exposed for coupling with a redistribution circuit that electrically couples at least one die contact to an extended contact such as a bumped contact. A wafer-level redistribution circuit interconnects a plurality of dice and includes a redistribution circuit for coupling between a die contact on one of the dice and a corresponding bumped contact. The wafer-level redistribution circuit further includes a bus conductor traversing each of the plurality of dice for electrically coupling with at least another one of the plurality of dice. At least one other conductor couples the redistribution circuit to the bus conductor.

Wafer-level redistribution circuit

Semiconductor assemblies having electrophoretically insulated vias

Methods for creating lined vias in semiconductor substrates. Using electrophoretic deposition techniques, micelles of a lining material are deposited on the wall of the via, reacting with the surface of the wall until the entire wall is covered by the lining material. The lining material is then fixed in place to form a layer lining the via. The lined via may then be filled with a desired material. For example, a via lined with an insulative material may be filled with a material such as copper to create an insulated conductive via through the substrate.

Methods for creating electrophoretically insulated vias in semiconductive substrates and resulting structures

A semiconductor component configured for wafer-level testing includes a semiconductor die having at least one die contact electrically exposed for coupling with a redistribution circuit that electrically couples at least one die contact to an extended contact such as a bumped contact. The component further includes a bus conductor that traverses at least a portion of the die and electrically mates with corresponding bus conductors on other similarly prepared components on the wafer. Functional and nonfunctional dice are identified on the wafer and the nonfunctional dice are isolated from the wafer-level testing grid. Following test, dice may be subsequently tested or moved to singulation wherein the die-to-die interconnection is interrupted, allowing wafer-level tested components to be conventionally assembled. A wafer may be retrofit with the wafer-level redistribution circuit for facilitating wafer-level testing without requiring customization of test fixtures or software for avoiding testing of nonfunctional dice.

Wafer-level testing apparatus and method

The use of a resist latent image alignment mark in lieu of using dedicated discrete alignment targets defined on a semiconductor wafer and the use of field oxide step heights for alignment during the fabrication of circuit devices are disclosed. A resist latent image alignment mark is formed in a layer of photoresist material and utilized to position a mask for exposing portions of the photoresist to a radiation source to pattern locations for active areas on a semiconductor substrate. A LOCOS isolation structure is then formed around the active areas. The isolation structure is formed such that the depth of the isolation structure is adjusted to a particular radiation source wavelength. The depth of the isolation structure can then be used as a diffraction grating for stepper alignment. Isolation structure height may also be used as a diffraction grating for stepper alignment.

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Star, ID, United States of America

Steven M McDonald