Fairchild Semiconductor Corporation

National Semiconductor Corporation

Other

Fairchild Semiconductor Co.

Steven M Macaluso

Julie Lynn Stultz

Nickole Gagne

Roy L Yarbrough

James B Boomer

Enrique O Rodriguez

Hrvoje Jasa

Oscar W Freitas

Ivan Duzevik

Michael L Fowler

James Joseph Morra

Richard W Cook

Stephen James O'Brien

Jani Kauppinen

John L Carpentier

A switch can be configured to receive a first signal at a first input and provide an output signal at an output, depending on a state of the switch. A switch state change can be delayed until an indication of a requested switch state different than a current switch state is received and the first signal reaches a threshold.

No pop switch

This document discusses, among other things, apparatus and methods including an analog-to-digital controller (ADC) configured to receive an enable signal and to provide an ADC output signal to control logic, wherein the control logic is configured to provide a control voltage to a control input of a switch. In an example, the control voltage includes the ADC output signal when the ADC output signal is below a first threshold or above a second threshold. In certain examples, the control logic is configured to transition the control voltage from the first threshold to the second threshold when the ADC output signal is between the first and second thresholds.

Audio device switching with reduced pop and click

This document discloses, among other things, a voltage clamp circuit where an output voltage equals an input voltage for at least a portion of a first range of input voltages, and where the output voltage is less than the input voltage for at least a portion of a second range of input voltages.

High voltage clamp circuit

This document discusses, among other things, apparatus and methods for passing a signal in a power down state. An example switch device can include a first depletion-mode transistor configured to pass an analog signal between a first node and a second node in a first state and to isolate the first node from the second node in a second state, a control circuit coupled to a control node of the first depletion-mode transistor and configured to isolate the control node from a first supply input in the first state and to couple the control node to the first supply input in the second state, and a tracking circuit configured to couple the control node of the first depletion-mode transistor to the first node during the first state and to isolate the control node of the first depletion-mode transistor from the first node in the second state.

Power down enabled analog switch

This document discusses, among other things, a compensation circuit configured to modulate a control voltage of a switch over a range of ambient temperatures during a conduction state of the switch to maintain a specified resistance between first and second nodes of the switch. The compensation circuit can include a temperature-insensitive resistor configured to provide a sense current, a current mirror configured to provide a mirror current using the sense current, and a temperature-sensitive resistor configured to provide the control voltage using the mirror current.

Stable ON-resistance switch circuit

This application discusses, among other things, switch circuit apparatus having power down protection and not requiring power up sequencing. An apparatus embodiment can include a first supply node coupled to a first input of a level shifting circuit via a protection circuit, a second supply node coupled to a second input of the level shifting circuit via a single pull-up transistor, and a switch including a control input, a first node, and a second node controllably isolated from the first node, wherein the control input is coupled to the level shifting circuit. The first and second inputs of the level shifting circuit can be coupled via a rectifier, and the protection circuit can be configured to power the first and second supply nodes to controllably isolate the first and second nodes from each other when a voltage of one of the first or second nodes exceeds a threshold.

Charge pump switch power down protection

A system and process for eliminating a control wire between logic systems that communicate with each other. In one embodiment, a system sends to a receiver a frequency that indicates a first mode. In the first mode a first data type may be sent. When the frequency is changed a second mode is indicated wherein a second data type may be sent. The receiver detects the frequency change and assumes the first or second mode as indicated.

Method and circuit for changing modes without dedicated control pin

A circuit that automatically, seamlessly connects the higher (or the lower) of two power supplies to an output is described. The circuit does not incur a one diode drop when the two power supplies are at about the same voltage levels, and the unused power supply draws no stand-by current. Cross coupled transistor and cross coupled inverters are employed.

Power latch

A MOSFET switch is disclosed that is driven on by a circuit that provides a constant gate to source voltage, Vgs, that is independent of the input voltage, the power supply and any logic signals. The constant Vgs is derived from a reference voltage and biases the MOSFET switch such that Ron is constant, or Rflatness is minimized. A minimized Rflatness provides a higher fidelity transfer of audio signals compared to prior art switches where Rflatness is greater.

Constant switch Vgs circuit for minimizing rflatness and improving audio performance

A circuit is described that when the power supply to circuits that control a pass transistor is at zero volts, the pass transistor configured as a voltage level translator remains off regardless of the voltages and changes in voltages at the ports connected to the pass transistor. Cross coupled transistors provide a mechanism where the higher of the port voltages is available to power circuitry that maintains the control input of the pass transistor in the off condition. The voltages at the ports may rise and fall relative to each other, but the control input of the pass transistor will keep the pass transistor off.

Power supply insensitive voltage level translator

A serializer/deserializer is disclosed with a flexible design that allows for sending data streams between computer systems where the power dissipation is markedly reduced by placing the serializer/deserializer in a standby, low power mode between the sending of data. Word data bits are framed and sent along with clock pulses that define when the bits may be reliably received. High speed, typically, CML logic is used for the transmission line drivers and together with the clock pulse, a data word is sent faster than the computer system can send the next word to the serializer/deserializer. The disclosure frames the word and detects the word end, whereupon the system is placed into the standby mode. In addition the serializer/deserializers may be placed in a master/slave arrangement where the slave can be arranged to use the master's clock to send word data bits back to the master.

Low power serdes architecture using serial I/O burst gating

A serializer is described that incorporates a register and a delay circuit for each serial bit. The serializer provides a timing signal that is generated and output simultaneously with the output of the data bit that ensures close timing alignment of the data bit and the timing signal. No clock is used. This allows the deserialzer/receiver to reliably receive the data bit. Each illustrative delay circuit is configured to trigger the next register/delay circuit to output the next sequential bit and its timing signal.

Clockless serialization using delay circuits

Box switches are stacked sharing a common current from power sources. The power sources may be current, voltage or a combination of such sources. In preferred embodiments, the transistor switches in the box switches may be paralleled by different polarity transistors that will act to better balance and make symmetrical the output signals. Capacitors may be used to smooth out residual noise voltage signals.

Dual output differential line driver using single current

A differential transmission line driver with supplemental current sources that overcome switching anomalies and EMU issues when the logic state of the driver is switching. During a logic transition, a current source, that is directed to the output of the driver, may be prevented from delivering its current. The present invention provides a supplemental current that is active during this transition period to supply the missing current. The present disclosure also details a common mode circuit that maintains a stable common mode output level to help control EMI issues when the power supply for the driver changes.

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Portland, ME, United States of America

Steven M Macaluso