Fairchild Semiconductor Corporation

Steven M Leibiger

Daniel J Hahn

Sunglyong Kim

Christopher Nassar

Gary M Dolny

James Hall

Ronald B Hulfachor

Michael Harley-Stead

Laurence M Szendrei

Julie Lynn Stultz

Tyler Daigle

Sam Zheng

Gary Sun

Mark Schmidt

Mark A Doyle

In certain examples an integrated circuit protection circuit can include a circuit module, and an isolation device. The isolation device can be configured to couple a ground node of the circuit module to a power ground in an on state, and to isolate the ground node of the circuit module from the power ground in an off state, wherein the isolation module is configured to enter the off state when the IC receives a negative input voltage.

Method and apparatus for integrated circuit protection

In one general aspect, a method can include implanting a first dopant, simultaneously, in a portion of a laterally diffused metal oxide semiconductor (LDMOS) device and in a portion of a resistor device included in a semiconductor device. The method can also include implanting a second dopant, simultaneously, in a portion of the LDMOS device and in a portion of a bipolar junction transistor (BJT) device in the semiconductor device.

Production of laterally diffused oxide semiconductor (LDMOS) device and a bipolar junction transistor (BJT) device using a semiconductor process

In one general aspect, a semiconductor processing method can include forming an N-type silicon region disposed within a P-type silicon substrate. The method can also include forming a field oxide (FOX) layer in the P-type silicon substrate where the FOX layer includes an opening exposing at least a portion of the N-type silicon region. The method can further include forming a reduced surface field (RESURF) oxide (ROX) layer having a first portion disposed on the exposed N-type silicon region and a second portion disposed on the FOX layer where the ROX layer includes a first dielectric layer in contact with the exposed N-type silicon region and a second dielectric layer disposed on the first dielectric layer. The method can further include forming a doped polysilicon layer having a first portion disposed on the first portion of the ROX layer and a second portion disposed on the second portion of the ROX layer.

Production of high-performance passive devices using existing operations of a semiconductor process

In one general aspect, an apparatus can include a channel region disposed in a semiconductor substrate, a gate dielectric disposed on the channel region and a drift region disposed in the semiconductor substrate adjacent to the channel region. The apparatus can further include a field plate having an end portion disposed between a top surface of the semiconductor substrate and the gate dielectric The end portion can include a surface in contact with the gate dielectric, the surface having a first portion aligned along a first plane non-parallel to a second plane along which a second portion of the surface is aligned, the first plane being non-parallel to the top surface of the semiconductor substrate and the second plane being non-parallel to the top surface of the semiconductor substrate.

LDMOS device with double-sloped field plate

Semiconductor devices and methods for making such devices are described. The semiconductor devices are made by providing a semiconductor substrate with an active region, providing a bulk oxide layer in a non-active portion of the substrate, the bulk oxide layer having a first thickness in a protected area of the device, providing a plate oxide layer over the bulk oxide layer and over the substrate in the active region, forming a gate structure on the active region of the substrate, and forming a self-aligned silicide layer on a portion of the substrate and the gate structure, wherein the final thickness of the bulk oxide layer in the protected area after these processes remains substantially the same as the first thickness. The thickness of the bulk oxide layer can be increased without any additional processing steps or any additional processing cost. Other embodiments are described.

Use of plate oxide layers to increase bulk oxide thickness in semiconductor devices

In one embodiment of the present invention an array of power transistors on a semiconductor chip has repeating patterns of two 'wave' gates which have alternating longer and shorter horizontal sections which are offset mirror images of each other together with a third straight horizontal section. Alternating source and drain regions lie between adjacent gates. Contacts are located adjacent each side of sections of the 'wave' gates which connect the ends of the horizontal sections of the &#x201c;wave&#x201d; gates.

Low on resistance CMOS 'wave' transistor for integrated circuit applications

A high voltage semiconductor device, such as a RESURF transistor, having improved properties, including reduced on state resistance. The device includes a semiconductor substrate with a drift region between source region and drain regions. The drift region includes a structure having a spaced trench capacitor extending between the source region and the drain region and a vertical stack extending between the source region and the drain region. When the device is in an on state, current flows between the source and drain regions; and, when the device is in an off/blocking state, the drift region is depleted into the stack.

PN junction and MOS capacitor hybrid resurf transistor

A CMOS device with polysilicon protection tiles is shown in FIG.. LOCOS regionsandseparate adjacent active regionsfromandfrom, respectively. On the upper surface of the LOCOS regionsare polysilicon tiles, respectively. At the corner of the gate polysiliconand the polysilicon tilesandare oxide spacers-. The polysilicon tileshave silicide layers. Other silicide layers-are on the tops of the source, drain and polysilicon gate. An insulation layercovers the substrate and metal contactsextend from the surface of the layerto the silicide layers on the source, gate and drain, respectively. The polysilicon tiles are made from the same layer of polysilicon as the gate and they are formed simultaneously with the gates. The intention of the polysilicon tiles is to reduce erosion of the field oxide between closely spaced active regions. In addition, the poly tiles themselves increase the thickness of the isolation between active silicon regions when it must serve as a self-aligned blocking layer for an ion implantation step.

Method for enhancing field oxide

A high voltage semiconductor device, such as a RESURF transistor, having improved properties, including reduced on state resistance. The device includes a semiconductor substrate; a source region and a drain region provided in the substrate; wherein the source region and the drain region are laterally spaced from each other; and a drift region in the substrate between the source region and the drain region. The drift region includes a structure having at least two spaced trench capacitors extending between the source region and the drain region; and further includes a stack having at least a first region of a first conductivity type, a second region of a second conductivity type, and a third region of the first conductivity type, wherein the stack extends between the source region and the drain region and between the at least first and second trench capacitors and in electrical connection to the first and second trench capacitors. When the device is in an on state, current flows between the source and drain regions through the second region of the second conductivity type; and, when the device is in an off/blocking state, the second conductivity region is depleted four ways into the first and third regions of the stack and into the first and second trench capacitors.

PN junction and MOS capacitor hybrid RESURF transistor

An array of power transistors on a semiconductor chip has serpentine gates separated by alternating source and drain regions. The gates combine rounded ends and rectangular sections joining the rounded ends. This geometry allows the metallization, in which the upper and lower metal layers are substantially congruent with each other, to have a design width that can be increased or decreased with the changes in width matched by the length of the rectangular sections thus allowing flexibility in the design of the power transistors.

Low on resistance CMOS transistor for integrated circuit applications

A process for forming a bipolar transistor where the doping implantation of the extrinsic base regions does not affect the emitter doping levels. The techniques is to not remove the photoresist layer used to define the poly emitter contact. The photoresist layer for defining the extrinsic base regions overlays the photoresist layer over the emitter poly. When the base photoresist is processed to expose the base regions the photoresist over the emitter poly remains in tact. In this arrangement the base implantation is prevented from driving through the emitter poly and affecting the doping levels in the emitter.

Single polisilicon emitter bipolar junction transistor processing technique using cumulative photo resist application and patterning

An emitter stack for a quasi-self-aligned bipolar (NPN or PNP) transistor is formed where two layers over the emitter of a silicon substrate are windowed in a manner to under cut the top layer thereby exposing the substrate material. The emitter polysilicon structure is then formed over the window and conformally extends into the undercut region thereby widening the emitter region and so reducing the distance between the edge of the emitter and the extrinsic base (the base link distance) and therefore reducing the total base resistance of the transistor.

Quasi self-aligned single polysilicon bipolar active device with intentional emitter window undercut

A structure of and a method for making an isolated NMOS transistor using standard BiCMOS processing steps and techniques. No additional masks and processing steps are needed for the isolated NMOS device relative to the standard process flow. A P-type substrate with an overlaying buried N-type layer overlaid with a buried p-type layer below a P-well is shown. An N-type region surrounds and isolates the P-well from other devices on the same wafer. N+ regions are formed in the p-well for the source and drain connections and poly or other such electrical conductors are formed on the gate, drain and source structures to make the NMOS device operational. Parasitic bipolar transistors are managed by the circuit design, current paths and biasing to ensure the parasitic bipolar transistors do not turn on.

Method and structure for BiCMOS isolated NMOS transistor

A resistor structure is disclosed that is constructed out of two layers of polysilicon. The intrinsic device is made using the top layer which is either a dedicated deposition, or formed as part of an existing process step such as a base epi growth in a BiCMOS flow. This poly layer can be made with a relatively high (greater than 2000 ohms per square) sheet resistance by appropriate scaling of the implant dose or by insitu doping methods. The resistor ends are formed by the addition of a bottom poly layer in a self aligned manner with a deposition which may already be part of the process sequence. The end result is that the intrinsic resistor body is formed of a single poly layer, while the ends are created out of two layers. These ends are thick enough so that standard silicide and contact etch processing may be added to the structure without special care. In addition, dedicated or already available implants may be incorporated into the resistor ends to ensure ohmic contacts from polysilicon to the silicide or the contact metal are achieved. These steps can produce an easily fabricated resistor structure with consistent, low resistance, ohmic end contacts, and intrinsic resistance of greater than 2000 ohms per square.

High value polysilicon resistor

An ESD protection device including a transistor structure with resistive regions located within active areas thereof. The transistor structure is formed of one or more MOS transistors, preferably N-type MOS transistors. The drain regions of the transistors are modified to reduce the conductivity of those resistive regions by preventing high carrier concentration implants in one or more sections of the drain regions. This is achieved by modifying an N LDD mask and the steps related thereto, as well as a silicide exclusion mask and the steps related thereto. The modifications result in the omission of N LDD dopant from the area immediately adjacent to the underlying channel. In addition, portions of a spacer oxide remain over the drain region to be formed. Subsequent implant and siliciding steps are effectively blocked by the spacer oxide that remains, leaving a low-density drain (LDD) charge carrier concentration in those regions, except where omitted. The resistivity of those resistive LDD regions is greater than the resistivity of the adjacent portions of the drain region. The result is more uniform turn-on of ESD transistor fingers in a protection device set without the need to add valuable layout space and without increased processing steps.

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Falmouth, ME, United States of America

Steven M Leibiger