Texas Instruments Corporation

Steven Loveless

Tathagata Chatterjee

YuGuo Wang

Jerry Doorenbos

Baher S Haroun

Srinath Mathur Ramaswamy

Lei Ding

Dok Won Lee

James Robert Todd

Andrew Derek Strachan

Wai Lee

Robert Stanley Grondalski

In a described example, a circuit includes a sensor circuit including multiple magnetic field sensors having respective sensor outputs. The magnetic field sensors are configured to provide magnetic field sensor signals at the respective sensor outputs representative of a measure of current flow through a conductive structure. A combiner interface has combiner inputs and a combiner output. The combiner inputs are coupled to the respective sensor outputs. The combiner interface is configured to provide an aggregate sensor measurement at the combiner output responsive to the magnetic field sensor signals, in which the aggregate sensor measurement is decoupled from magnetic fields generated responsive to the current flow through the conductive structure.

Magnetic current sensing

A system comprises a noise generator circuit and a noise envelope detector circuit. The noise generator circuit comprises a first amplifier including a single transistor pair that is operable to generate 1/f noise, an output amplifier coupled to the first amplifier and configured to generate a 1/f noise signal as a function of the 1/f noise. The noise envelope detector circuit comprises a low pass filter operable to pass low frequency signals of the 1/f noise signal as a filtered 1/f noise signal, and a second amplifier or a comparator coupled to the low pass filter and operable to output a direct current (DC) voltage signal according to an envelope of the filtered 1/f noise signal, where the DC voltage signal is a function of an envelope of the filtered 1/f noise signal.

Direct current measurement of 1/f transistor noise

In various examples, a method and apparatus are provided to achieve dynamic biasing to mitigate electrical stress. Described examples include a device includes a first resistor portion having a first terminal and a second terminal, and a second resistor portion having a third terminal and a fourth terminal. The device also includes a well in a substrate proximate to the first resistor portion and the second resistor portion and an insulating layer between the well and the first resistor portion and the second resistor portion. The device also includes a transistor having a control terminal coupled to the second terminal of the first resistor portion and the third terminal of the second resistor portion, the transistor having a first current-handling terminal coupled to a first voltage and a second current-handling terminal coupled to a current source and to the well.

Dynamic biasing to mitigate electrical stress in integrated resistors

An analog-to-digital converter (ADC) comprising successive approximation circuitry, a capacitive analog-to-digital converter (CDAC), and capacitor mismatch measurement circuitry. The successive approximation circuitry is configured to control conversion of an analog signal to a digital value. The CDAC is coupled to the successive approximation circuitry. The CDAC includes a plurality of capacitors. The capacitor mismatch measurement circuitry is coupled to the CDAC. The capacitor mismatch measurement circuitry includes a first oscillator circuit, a second oscillator circuit, and counter circuitry. The first oscillator circuit is configured to oscillate at a frequency determined by a capacitance of one of the capacitors. The second oscillator circuit is configured to generate a predetermined time interval. The counter circuitry is configured to count a number of cycles of oscillation of the first oscillator in the predetermined time interval.

Capacitive mismatch measurement

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Sachse, TX, United States of America

Steven Loveless