International Business Machines Corporation

Pioneer Hi-bred International, Inc.

Textron Systems Corporation

Steven Lorenz Wright

Bing Dang

John Ulrich Knickerbocker

Yang Liu

Joshua M Rubin

Bucknell Chapman Webb

Jerry M Woodall

Sandip Tiwari

Lawrence Alfred Clevenger

Timothy Harrison Daubenspeck

Timothy Dooling Sullivan

Paul Stephen Andry

Peter Daniel Kirchner

Joana S B T Maria

Thomas Anthony Wassick

Krystyna Waleria Semkow

Raymond R Horton

Yu Luo

Thomas N Jackson

Ekta Misra

Cornelia Tsang Yang

Steven Edward Millman

George John Scott

Gary Lafontant

Richard Ian Kaufman

Kenneth C Ho

Paul F Greier

Wolfgang Sauter

Paul Michael Solomon

Arvind Kumar

Edmund Juris Sprogis

Kamal Kumar Sikka

Chai Wah Wu

Roland Welle

Raschid Jose Bezama

Jeremy H Burroughes

Cornelia K Tsang

Gerhard Robert Thompson

S Jay Chey

Ian D Melville

Alphonso Philip Lanzetta

Xiaojin Wei

Leena Paivikki Buchwalter

Kai R Schleupen

Robin A Susko

Michael A Tischler

Mark S Milshtein

George D Pettit

John Batey

Joana Sofia Branquinho Teresa Maria

Alan C Warren

Michael Patrick Mastro

William H Price

Lavanya Turlapati

Masanori Murakami

Kenneth F Latzko

Steven T Berman

Ron Ridgeway

Alfred Grill

Charles Leon Arvin

Xiao Hu Liu

Chandrasekhar Narayan

David L Questad

Bruce Kenneth Furman

David L Johnson

Wiren Dale Becker

Shui-Chih Alan Lien

Gregory M Fritz

Thomas Edward Lombardi

Eric Peter Lewandowski

Frederick Cole Mintzer

Jonathan E Lightner

Mounir Meghelli

James Edward Christensen

Gordon Wesley Braudaway

Kevin Wilson Warren

Pedro A Chalco

Michael James Cordes

Donald M DeCain

Ronald Franklin Marks

C Fred Hood

James A Janni

William Sylvester Niebur

Paul M Alt

Albert Nessim Cazes

Benal Lee Owens, Jr

James J Rosenberg

Piyas Bal Chowdhury

Thomas B Brumback

Federico Valverde

A flip chip device and methods for fabrication are provided. An interconnect layer for a device include a plurality of solder bumps arranged within the interconnect layer. A first subset of the plurality of solder bumps has a first cross-sectional area, where the first subset is arranged along a first position at a first edge of the interconnect layer. A second subset of the plurality of solder bumps has a second cross-sectional area, where the second subset is arranged at a second position of the interconnect layer. A third subset of the plurality of solder bumps is arranged between the first position and the second position, where the third subset has a plurality of cross-sectional areas.

Electronic package with varying interconnects

Embodiments of one or more high bandwidth chips (HB chips), e.g., high bandwidth memories (HBMs), are mounted on a module substrate. The HB chips/HBMs each have one or more HBM parallel communication interfaces (HB chip PHYs or HBM PHYs, respectively) that are connected to a companion PHY through a compatible companion PHY parallel connection that enable communication between the HBM PHY and the companion PHY. A companion PHY parallel link connection connects to a SERDES parallel connection of a SERDES. The SERDES converts parallel data/information at the SERDES parallel connection to serial data/information at a SERDES serial connection, and visa-versa, that enables efficient high bandwidth data transfer over longer distances. Alternative embodiments are disclosed.

Interconnection structures for high bandwidth data transfer

A pillar structure is provided. The pillar structure includes a plurality of pillars. Each of the pillars include a capping material layer formed in a pit etched into a template wafer, a conductive plug formed on the capping material layer, a base layer formed on the conductive plug, and an attach material layer formed on the base layer. The pillars are joined vertically together to form the pillar structure.

Transferrable pillar structure for fanout package or interconnect bridge

A multi-chip package structure includes a chip interconnect bridge, a fan-out redistribution layer structure, a first integrated circuit chip, and a second integrated circuit chip. The chip interconnect bridge includes contact pads disposed on a top side of the chip interconnect bridge. The fan-out redistribution layer structure is disposed around sidewalls of the chip interconnect bridge and over the top side of the chip interconnect bridge. The first and second integrated circuit chips are direct chip attached to an upper surface of the fan-out redistribution layer structure, wherein the fan-out redistribution layer structure includes input/output connections between the contact pads on the top side of the chip interconnect bridge and the first and second integrated circuit chips.

Multi-chip package structures having embedded chip interconnect bridges and fan-out redistribution layers

Embodiments of the present invention are directed to a liquid delivery apparatus. A non-limiting example of the apparatus includes a substrate including a cavity formed in a surface of the substrate. The apparatus can also include a membrane disposed on the surface of the substrate covering an opening of the cavity. The apparatus can also include a hydrophobic layer disposed on the membrane. The apparatus can also include a seal disposed between the membrane and the substrate, wherein the seal surrounds the opening of the cavity. The apparatus can also include an electrode layer coupled to the membrane.

Fluid delivery device with hydrophobic surface

Techniques are provided for constructing multi-chip package structures. For example, a multi-chip package structure includes a package substrate, an interconnect bridge device, a first chip package, and a second chip package. The first chip package includes a first redistribution layer structure, and a first integrated circuit chip connected to the first redistribution layer structure. The first redistribution layer structure is connected to the interconnect bridge device and to the package substrate. The second chip package includes a second redistribution layer structure, and a second integrated circuit chip connected to the second redistribution layer structure. The second redistribution layer structure is connected to the interconnect bridge device and to the package substrate. The interconnect bridge device includes wiring to provide package-to-package connections between the first and second chip packages.

Multi-chip package structures with discrete redistribution layers

A multi-chip package structure includes a package substrate, an interconnect bridge device, first and second integrated circuit chips, and a connection structure. The first integrated circuit chip is flip-chip attached to at least the interconnect bridge device. The second integrated circuit chip is flip-chip attached to the interconnect bridge device and to the package substrate. The interconnect bridge device includes (i) wiring that is configured to provide chip-to-chip connections between the first and second integrated circuit chips and (ii) an embedded power distribution network that is configured to distribute at least one of a positive power supply voltage and a negative power supply voltage to at least one of the first and second integrated circuit chips attached to the interconnect bridge device. The connection structure (e.g., wire bond, injection molded solder, etc.) connects the embedded power distribution network to a power supply voltage contact of the package substrate.

Multi-chip package structure having high density chip interconnect bridge with embedded power distribution network

Techniques are provided for constructing multi-chip package structures using pre-positioned interconnect bridge devices that are fabricated on a bridge wafer. For example, integrated circuit chips are mounted to a bridge wafer which is formed to have a plurality of pre-positioned interconnect bridge devices, wherein at least two integrated circuit chips are joined to each interconnect bridge device, and wherein each interconnect bridge device includes wiring to provide chip-to-chip connections between the integrated circuit chips connected to the interconnect bridge device. A wafer-level molding layer is formed on the bridge wafer to encapsulate the integrated circuit chips mounted to the bridge wafer. The interconnect bridge devices are released from the bridge wafer. The wafer-level molding layer is then diced to form a plurality of individual multi-chip modules.

Multi-chip package structures formed by joining chips to pre-positioned chip interconnect bridge devices

A multi-chip package structure includes a chip interconnect bridge, a fan-out redistribution layer structure, a first integrated circuit chip, and a second integrated circuit chip. The chip interconnect bridge includes contact pads disposed on a top-side of the chip interconnect bridge. The fan-out redistribution layer structure is disposed around sidewalls of the chip interconnect bridge and over the top-side of the chip interconnect bridge. The first and second integrated circuit chips are direct chip attached to an upper surface of the fan-out redistribution layer structure, wherein the fan-out redistribution layer structure includes input/output connections between the contact pads on the top-side of the chip interconnect bridge and the first and second integrated circuit chips.

Electromechanical substance delivery devices are provided which implement low-power electromechanical release mechanisms for controlled delivery of substances such as drugs and medication. For example, an electromechanical device includes a substrate having a cavity formed in a surface of the substrate, a membrane disposed on the surface of the substrate covering an opening of the cavity, and a seal disposed between the membrane and the surface of the substrate. The seal surrounds the opening of the cavity, and the seal and membrane are configured to enclose the cavity and retain a substance within the cavity. An electrode structure is configured to locally heat a portion of the membrane in response to a control voltage applied to the electrode structure, and create a stress that causes a rupture in the locally heated portion of the membrane to release the substance from within the cavity.

Microchip substance delivery devices

A digital biomedical device includes a substrate forming a reservoir, a membrane comprising a first layer and a second layer having a strain therebetween, the membrane sealing the reservoir, and a controller configured to activate the membrane and release at least a portion of the strain causing the membrane curl and open the reservoir.

Drug delivery device having a cavity sealed by a pressurized membrane

A digital biomedical device includes a substrate forming a cavity, a seal formed around the cavity, a lid coupled to the substrate by the seal, a reactive metal structure comprising a plurality of metal layers, wherein the reactive metal structure is a component of at least one of the substrate and the lid, a metal trace configured to initiate a self-propagating reaction between the plurality of metal layers of the reactive metal structure and release contents of the cavity, and a power supply configured to apply an electric current to the metal trace.

Delivery device including reactive material for programmable discrete delivery of a substance

An apparatus includes a substrate mechanically and electrically connected on one side of the substrate to multiple metallic probes in one or more arrays and includes the multiple metallic probes in the one or more arrays. In a method, multiple pits may be formed in an array on a first substrate. The pits have a pyramidal shape. A release layer is formed on the first substrate and covers surfaces of the pits. Probe tips are formed in the pits on the first substrate. The probe tips are formed from rigid conductive material. Multiple pillars are formed from rigid conductive material. The pillars are electrically and mechanically connected to a second substrate and to the probe tips. Release is caused of the probe tips from the first substrate, wherein the pillars and probe tips are connected to the second substrate and together form an array of rigid and conductive probes.

Transdermal sensing probes and smart patch systems using same

A probe head that contains a coining surface and a plurality of probe tips integrated on a same side of the probe head is provided. The probe head has a first portion and a laterally adjacent second portion, wherein the first portion of the probe head contains the coining surface, and the second portion of the probe head contains the plurality of the probe tips. Each probe tip may, in some embodiments, extend outwards from a probe pedestal that is in contact with the second portion of the probe head. The probe head is traversed across the surface of a semiconductor wafer containing a plurality of solder bump arrays such that the coining surface contacts a specific array of solder bumps prior to contacting of the same specific array of solder bumps with the probe tips.

Integrated self-coining probe

Growing community of inventors

Cortlandt Manor, NY, United States of America

Steven Lorenz Wright