Tandy Corporation

Radioshack Corporation

Steven Leininger

The computer system of this invention has a simple processing unit for providing most data processing by the computer system under control of a read-only memory which contains instructions and other data for the CPU. The system also includes a random access memory, a keyboard, a video terminal, and a port device in the form of a tape recorder/player. A master clock initiates timing used throughout the system. A multi-line data bus interconnects the CPU and the different memories of the system including the keyboard and the video RAM. Bi-directional communication is possible on the data bus. The addressing of these different memories is by way of an address bus from the CPU, which is a uni-directional bus. Data to be operated upon is stored in the random access memory. The keyboard is used for inputting data to the CPU and the video terminal is used for displaying data. Features of the present invention include a special reset scheme for the CPU, a multiplexing scheme for addressing the RAM, a technique for simply altering the control to provide capabilities of different capacity memories, alternate display of characters to provide either a 32-character line or a 64-character line, an improved keyboard selection scheme, and improved video processing means.

Memory address decoding system

The computer system of this invention has, a simple processing unit for providing most data processing by the computer system under control of a read-only memory which contains instructions and other data for the CPU. The system also includes a random access memory, a keyboard, a video terminal, and a port device in the form of a tape recorder/player. A master clock initiates timing used throughout the system. A multi-line data bus interconnects the CPU and the different memories of the system including the keyboard and the video RAM. Bi-directional communication is possible on the data bus. The addressing of these different memories is by way of an address bus from the CPU, which is a uni-directional bus. Data to be operated upon is stored in the random access memory. The keyboard is used for inputting data to the CPU and the video terminal is used for displaying data. A reset switch is operable by the operator of the computer system to reset the system by forcing the CPU to a known address. Also, at power-up, the CPU is reset starting at a preselected address. The CPU may also be restarted by means of the manual reset switch starting with execution of instructions from a predetermined address in the ROM. The reset switch couples to the interrupt input of the microprocessor. The power-up circuit couples to the reset input of the microprocessor.

Computer

The computer system of this invention has, as the heart of the system, a simple processing unit for providing most data processing by the computer system under control of a read-only memory which contains only instructions and other data for the CPU. The system also includes a random access memory, a keyboard, a video terminal, and a port device in the form of a tape recorder/player. A master clock initiates timing used throughout the system. A multi-line data bus interconnects the CPU and the different memories of the system including the keyboard and the video RAM. Bi-directional communication is possible on the data bus. The addressing of these different memories is by way of an address bus from the CPU, which is a uni-directional bus. Data to be operated upon is basically stored in the random access memory. The keyboard is used for inputting data to the CPU and the video terminal is used for displaying data. Features of the present invention include a special reset scheme for the CPU, a multiplexing scheme for addressing the RAM, a technique for simply altering the control to provide capabilities of different capacity memories, alternate display of characters to provide, for example, either a 32-character line or a 64-character line, an improved keyboard selection scheme, and improved video processing means.

In a computer system operating under read only memory control and having a keyboard, a video terminal, and a port device in the form of a tape recorder/player, an improved apparatus for alpha-numeric/graphic display in which the outputs of respective character and graphic generators couple to respective first and second shift registers with the shift registers being controlled by first and second gate means in a manner to enable clocking of the first shift register when the type code indicates alpha-numeric display and enabling clocking of the second shift register when the type code indicates graphic display.

Apparatus for alpha-numeric/graphic display

The computer system of this invention has a simple processing unit for providing most data processing by the computer system under control of a read-only memory which contains instructions and other data for the CPU. The system also includes a random access memory, a keyboard, a video terminal, and a port device in the form of a tape recorder/player. A master clock initiates timing used throughout the system. A multi-line data bus interconnects the CPU and the different memories of the system including the keyboard and the video RAM. Bi-directional communication is possible on the data bus. The addressing of these different memories is by way of an address bus from the CPU, which is a uni-directional bus. Data to be operated upon is stored in the random access memory. The keyboard is used for inputting data to the CPU and the video terminal is used for displaying data. Features of the present invention include a special reset scheme for the CPU, a multiplexing scheme for addressing the RAM, a technique for simply altering the control to provide capabilities of different capacity memories, alternate display of characters to provide, either a 32-character line or a 64-character line, an improved keyboard selection scheme, and improved video processing means.

Memory addressing system

Video processing system

The computer system of this invention has, as the heart of the system, a simple processing unit for providing most data processing by the computer system under control of a read-only memory which contains only instructions and other data for the CPU. The system also includes a random access memory, a keyboard, a video terminal, and a port device in the form of a tape recorder/player. A master clock initiates timing used throughout the system. A multi-line data bus interconnects the CPU and the different memories of the system including the keyboard and the video RAM. Bi-directional communication is possible on the data bus. The addressing of these different memories is by way of an address bus from the CPU, which is a uni-directional bus. Data to be operated upon is basically stored in the random access memory. The keyboard is used for inputting data to the CPU and the video terminal is used for displaying data. Features of the present invention include a special reset scheme for the CPU, a multiplexing scheme for addressing the RAM, techniques for simply altering the control to provide capabilities of different capacity memories, alternate display of characters to provide, for example, either a 32-character line or a 64-character line, an improved keyboard selection scheme, and improved video processing means.

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Arlington, TX, United States of America

Steven Leininger