Cadence Design Systems, Inc.

Denali Software, Inc.

Hewlett-packard Development Company, L.p.

Hewlett-packard Company

Steven Lee Shrader

Michael McKeon

Robert A Rust

Barry J Oldfield

Christopher W Johansson

Samitinjoy Pal

Christine Grund

Art Gmurowski

Anujan Varma

Robert Alan Reid

Marc Greenberg

Anne Espinoza

Ashwin Matta

Mohit Mittal

Wendy Bishop

A method for detecting a data bit inversion (DBI) error in a memory system is disclosed. The method and system comprise calculating an error correcting code (ECC) from each of the 8 beats of a burst of data such that no more than one bit per byte is included in each ECC calculation. The method and system further include determining if there is an inversion of one byte in the burst.

Method and apparatus for detecting or correcting multi-bit errors in computer memory systems

A system and method are provided for efficient allocation of data in a memory array having regions of varying storage reliability. Storage locations for bands of data are selectively allocated in a manner which evenly distributes the probability of error in the data when stored in the memory array in spite of the varying storage reliability. A distribution controller is provided to effect such distribution of data to maintain a collective error rate of each data band within a preselected or predetermined range. The system and method also generally provide for storing at least a first and a second data band in different corresponding sets of storage channels. The system and method also generally provide for at least one of the data bands being stored in regions of differing reliability across the set of storage channels therefor.

System and method for allocating data in memory array having regions of varying storage reliability

An invention is provided for dynamically configurable error correction. The invention includes receiving a check code configuration signal, which indicates a particular level of error detection. A check code generator is configured to generate check codes based on the particular level of error detection indicated by the check code configuration signal. In addition, an error locator configuration signal is received that indicates a particular level of error addressing, and an error locator is configured to produce addresses of errors in a set of data based on the particular level of error addressing indicated by the error locator configuration signal.

Method and apparatus for dynamically configurable multi level error correction

An invention is provided for improving performance in block based non-volatile memory when performing random small write operations. When requests for small page updates are received for a memory page currently storing data, the updated page data is written to a reserve memory page. The reserve memory page can be in the same memory block as the target memory page, or in an associated reserve memory block. In addition, the associated logical page address is temporarily remapped to the reserve page. Later, when time permits, the page data for the block can be reorganized into continuous pages in a new block.

Method and apparatus for improving small write performance in a non-volatile memory

An invention is provided for parallel ECC error location in a memory. The invention includes partitioning a set of field elements into w partitions. Then, for each of the w partitions of field elements, i) providing a set of r different field elements of the partition to r parallel search element. Next, in operation ii), each parallel search element computes a sum that is based on a set of coefficients of an error locator polynomial and the field element provided to the particular parallel search element. The set of field elements is advanced r field elements in GF(2), and operations i) through iii) are repeated using the next r different field elements of the partition.

Method and apparatus for parallel ECC error location

An invention is provided for a reactive placement controller for interfacing with a banked memory storage. The reactive placement controller includes a read/write module, which is coupled to a command control module for a banked memory device. A command queue is included that comprises a plurality of queue entries coupled in series, with a top queue entry coupled to the read/write module. Each queue entry is capable of storing a memory command. Each queue entry includes its own queue control logic that functions to control storage of new memory commands into the command queue to reduce latency of commands in the command queue.

Reactive placement controller for interfacing with banked memory storage

Fault tolerant data storage systems and methods of operating a fault tolerant data storage system are presented. In one aspect of the invention, a fault tolerant data storage system comprises: a plurality of coupled components individually including: an interface adapted to couple with a data connection and to selectively receive a plurality of transactions from the data connection; transaction processing circuitry coupled with the interface and configured to process transactions received from the interface; and analysis circuitry configured to detect error conditions within the transactions and to prevent entry of transactions individually including an error condition into the respective component responsive to the detection.

Data storage systems and methods

A port independent data transaction interface for multi-port devices is provided. The port independent data transaction interface includes a command channel that receives command data and a source id. The source id indicates a source device that transmitted the command data. In addition, a data-in channel is included that receives write data and a write source id. Similar to the source id, the write source id indicates a source device that transmitted the write data. The port independent data transaction interface further includes a data-out channel that provides read data and a read id. The read id indicates a source device that transmitted a read command corresponding to the read data. The port independent data transaction interface utilizes the source id to associate command data with corresponding write data and read data.

Port independent data transaction interface for multi-port devices

An interface for sending write data, write control signals and write data between a memory controller and a double data rate (DDR) memory with the appropriate timing relationships so that the write data can be reliably written in the DDR memory. Also, an interface for reliably capturing read data received from the DDR memory during a read operation.

Input/output cells for a double data rate (DDR) memory controller

A memory controller is provided. The memory controller includes an initiator block configured to arbitrate requests corresponding to data from multiple ports. The initiator block includes an arbitration module configured to consider a latency factor and a bandwidth factor associated with the data from a port to be selected for processing. A state machine is in communication with the arbitration module. The state machine is configured to generate a signal to the arbitration module that is configured to select the data associated with the port based upon the latency factor and the bandwidth factor. Task status and completion circuitry configured to calculate the bandwidth factor based upon previous data selected from the port is included in the initiator block. The task status and completion circuitry is further configured to transmit the calculated bandwidth factor to the state machine. A method for arbitrating across multiple ports is also provided.

Method and apparatus for multi-port memory controller

A controller is presented comprising one or more initiators coupled to one or more targets via a transaction bus and a corresponding number of data busses. The initiator(s) receive transaction requests from external logic, buffer the transaction and assign it a unique identifier, which is passed to an appropriate target via the transaction bus. The targets receive and queue the unique identifier until it can process the transaction, at which time it prompts the initiator to provide it the buffered transaction via a data bus dedicated to the target.

Method and apparatus to concurrently operate on multiple data movement transactions in a disk array subsystem

Circuitry for programming the amount of delay applied to an input signal, the circuitry performing the method of determining the number of delay elements required to capture a clock cycle, receiving a programmable delay value and calculating the number of delay elements required to delay a clock signal by the received delay value and delaying the clock signal by the number of delay elements required to delay the clock signal by the programmable delay value.

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Meridian, ID, United States of America

Steven Lee Shrader