Cray Incorporated

Cray Research, Inc.

Intel Corporation

Silicon Graphics, Incorporated

Leland Stanford Junior University

Nvidia Corporation

Steven Lee Scott

Dennis Charles Abts

Robert L Alverson

William James Dally

Steven M Oberlin

Gregory J Faanes

Edwin Froese

Richard E Kessler

Gregory J Hubbard

Michael A Parker

Eric Carl Fromm

Gregory Michael Thorson

Aaron Forest Godfrey

William T Moore, Jr

Gerald A Schwoerer

James Robert Kohn

Eric P Lundberg

Daniel L Kunkel

Abdulla Bataineh

Timothy J Johnson

Stephen William Keckler

Brucek Kurdo Khailany

Randal Steven Passint

Richard D Pribnow

John J Kim

Howard Pritchard

Peter G Logghe

Robert Baird

Brick Stephenson

Chris Dickson

Richard Eugene Kessler

William A Huffman

Laurence S Kaplan

David Mizell

Roger A Bethard

Greg Thorson

Kelly J Marquardt

Michael L Anderson

Michael F Ringenburg

Ram Gupta

Troy A Johnson

Steve Reinhardt

Karlon West

Skef Iterum

Subbarao Palacharla

Gregory B Titus

Sung-Eun Choi

A multiprocessor computer system comprises a first node operable to access memory local to a remote node by receiving a virtual memory address from a requesting entity in node logic in the first node. The first node creates a network address from the virtual address received in the node logic, where the network address is in a larger address space than the virtual memory address, and sends a fast memory access request from the first node to a network node identified in the network address.

Extended fast memory access in a multiprocessor computer system

A multiprocessor computer system comprises a dragonfly processor interconnect network that comprises a plurality of processor nodes, a plurality of routers, each router directly coupled to a plurality of terminal nodes, the routers coupled to one another and arranged into a group, and a plurality of groups of routers, such that each group is connected to each other group via at least one direct connection.

Dragonfly processor interconnect network

An integrated circuit device comprises pin resources, a memory controller circuit, a network interface controller circuit, and transmitter circuitry. The pin resources comprise pads coupled to off-chip pins of the integrated circuit device. The memory controller circuit comprises a first interface and the network interface controller circuit comprises a second interface. The transmitter circuitry is configurable to selectively couple either a first signal of the first interface or a second signal of the second interface to a first pad of the pin resources based on a pin distribution between the first interface and the second interface.

System and method for configuring a channel

A system and method for routing in a high-radix network. A packet is received and examined to determine if the packet can be routed adaptively. If the packet can be routed adaptively, the packet is routed adaptively, wherein routing adaptively includes selecting a column, computing a column mask, routing the packet to the column; and selecting an output port as a function of the column mask. If the packet can be routed deterministically, routing deterministically, wherein routing deterministically includes accessing a routing table to obtain an output port and routing the packet to the output port from the routing table.

Flexible routing tables for a high-radix router

A data-processing system and method for performing collective operations. Some embodiments provide a plurality of leaf software processes, a plurality of collective engines (CEs), and a network operatively coupled to the plurality of CEs, wherein collective operations messages are sent between CEs. Each of the plurality of hierarchies includes a root, leaf CEs, and one or more intermediate levels of CEs between the root and the leaf CEs. Each CE except the root is configured to have a parent CE, and each non-leaf CE in the hierarchy that is not the root CE and not one of the leaf CEs has one or more child CEs. Data is sent from software processes to one or more of the plurality of CEs, and data is received to one or more software processes from one or more of the plurality of collective engines. The root CE outputs a final result.

Collective engine method and apparatus

A method and system for software emulation of hardware support for multi-threaded processing using virtual hardware threads is provided. A software threading system executes on a node that has one or more processors, each with one or more hardware threads. The node has access to local memory and access to remote memory. The software threading system manages the execution of tasks of a user program. The software threading system switches between the virtual hardware threads representing the tasks as the tasks issue remote memory access requests while in user privilege mode. Thus, the software threading system emulates more hardware threads than the underlying hardware supports and switches the virtual hardware threads without the overhead of a context switch to the operating system or change in privilege mode.

Software emulation of massive hardware threading for tolerating remote memory references

A system and method are provided for configuring a plurality of pin resources. The method includes identifying a plurality of pin resources of a primary application specific integrated circuit (ASIC) device and configuring the plurality of pin resources based on a pin distribution between a first interface and a second interface, where the first interface provides a first communication path between the primary ASIC device and a first device, and the second interface provides a second communication path between the primary ASIC device and a second device.

A multiprocessor computer system comprises a sending processor node and a receiving processor node. The sending processor node is operable to send packets comprising part of a message to a receiver, to maintain a message buffer entry in the sender comprising the sent packets, to track acknowledgment from the receiver that sent packets have been received; to maintain a timer indicating the time since message data has been sent, and to resend packets not acknowledged upon the timer reaching a timeout state. The receiving processor node is operable to send acknowledgement to the sender that received packets have been received, to track packets using a received message table to track which packets comprising part of the message have been received and whether all packets in the message have been received, and to process packets once all packets in a message are received to reassemble the received message.

Reliable message transport network

A multiprocessor computer system comprises a sending processor node and a receiving processor node. The sending processor node is operable to send packets comprising part of a message to a receiver, and to send a message complete packet after all packets in the message are sent. The message complete packet includes an indicator of the number of packets in the message, and the message is recognized as complete in the receiver once the number of packets indicated in the message complete packet have been received for the message. The sender tracks acknowledgment from the receiver of receipt of the sent packets; and notifies the receiver when it has received all packets comprising a part of the message.

One-way message notification with out-of-order packet delivery

A processor core, comprises one or more vector units operable to change between a fine-grained vector mode having a shorter maximum vector length and a coarse-grained vector mode having a longer maximum vector length. Changing vector modes comprises halting all instruction stream execution in the core, flushing one or more registers in a register space, reconfiguring one or more vector registers in the register space, and restarting instruction execution in the core.

Configurable vector length computer processor

A multiprocessor computer system has a plurality of first processors having a first addressable memory space, and a plurality of second processors having a second addressable memory space. The second addressable memory space is of a different size than the first addressable memory space, and the first addressable memory space and second addressable memory space comprise a part of the same common address space.

Multiprocessor system having processors with different address widths and method for operating the same

An atomic memory operation cache comprises a cache memory operable to cache atomic memory operation data, a write timer, and a cache controller. The cache controller is operable to update main memory with one or more dirty atomic memory operation cache entries stored in the cache memory upon expiration of the write timer, and is further operable to update main memory with one or more dirty atomic memory operation cache entries stored in the cache memory upon eviction of the one or more dirty atomic memory operation cache entries from the cache memory.

Atomic memory operation cache protocol with opportunistic combining

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Eau Claire, WI, United States of America

Steven Lee Scott