Motorola Corporation

North American Philips Corporation

Philips Electronics North America Corporation

U.S. Philips Corporation

Steven L Merchant

Robert W Baird

Emil Arnold

Phillipe Dupuy

Ronald D Pinker

Peter W Shackle

Arnold, Emil

A field effect transistor ( ) has an array of transistors ( ) made up of bonding pads ( ) and sub-arrays of transistors ( ). The bonding pads ( ) are distributed between the sub-arrays of transistors ( ) to reduce the maximum temperature that any portion of the FET ( ) is exposed to while the FET ( ) is in a conducting state. A similar effect can be appreciated by adjusting the threshold voltage or pinch-off resistance of the transistors in a portion ( ) of an array of transistors ( ).

Field effect transistor having differing power dissipation across an array of transistors

Field effect transistor and method of making

A semiconductor device (10) is formed in a semiconductor substrate (11) and an epitaxial layer (14). The semiconductor device includes a p-type body region (16), a source region (17), a channel region (19), and a drain region (34) formed in the epitaxial layer (14). A doped region (13) is formed in the semiconductor substrate (11) to reduce the drift resistance of the semiconductor device (10). The drain region (34) is formed from a plurality of doped regions (30-33) that can be formed with high energy implants.

Semiconductor device and method of making

A field effect transistor (30) has an array of transistors (31) made up of bonding pads (45-47) and sub-arrays of transistors (41-43). The bonding pads (45-47) are distributed between the sub-arrays of transistors (41-43) to reduce the maximum temperature that any portion of the FET (30) is exposed to while the FET (30) is in a conducting state. A similar effect can be appreciated by adjusting the threshold voltage or pinch-off resistance of the transistors in a portion (101) of an array of transistors (95).

Method of changing the power dissipation across an array of transistors

A semiconductor device (10) is formed in a semiconductor substrate (11) and an epitaxial layer (14). The semiconductor device includes a p-type body region (16), a source region (17), a channel region (19), and a drain region (102) formed in the epitaxial layer (14). Doped regions (20,22) are formed in the epitaxial layer (14) that contain dopant of a conductivity type that is opposite to the epitaxial layer (14). The doped regions (20,22) divide the epitaxial layer (14) to provide or define doped regions (21,23). The doped regions (20,22) are formed from a plurality of doped regions (30,31,32,33) that can be formed with high energy implants.

Method of making a semiconductor device

The present invention is directed to a thin film transistor having a linear doping profile between the gate and drain regions. This is constructed in a particular manner in order to achieve a thin film transistor having a significantly high breakdown voltage of the order of 700 to 900 volts, much greater than that achieved in the prior art.

High voltage thin film transistor having a linear doping profile

A Semiconductor-On-Insulator (SOI) device includes a semiconductor substrate, a buried insulating layer on the substrate, and a lateral MOSFET on the buried insulating layer. The MOSFET includes a semiconductor surface layer on the buried insulating layer and has a source region of a first conductivity type, a channel region of a second conductivity type opposite to that of the first, an insulated gate electrode over the channel region and insulated therefrom, a lateral drift region of the second conductivity type, and a drain region of the first conductivity type laterally spaced apart from the channel region by the drift region. A semiconductor linkup region of the first conductivity type is provided between the channel region and the drift region and extends substantially through the semiconductor surface layer, and the source region of the device is electrically coupled to the drift region. This device configuration is particularly useful in providing a high-voltage p-channel MOS transistor using thin SOI high-voltage technology normally associated with fabricating n-channel devices.

High-voltage lateral MOSFET SOI device having a semiconductor linkup

A lateral thin-film silicon-on-insulator (SOI) device includes a lateral semiconductor device such as a diode or MOSFET provided in a thin semiconductor film on a thin buried oxide. The lateral semiconductor device structure includes at least two semiconductor regions separated by a lateral drift region. By providing a substantially linear lateral doping profile in the lateral drift region, and by providing a conductive field plate on a linearly-graded top oxide insulating layer, a device structure is obtained in which conduction losses can be reduced without reducing breakdown voltage.

Lateral thin-film SOI devices with linearly-graded field oxide and

This application is directed to an improved thin film SOI device in which a gate region extends over a thin layer of silicon having a lateral linear doping region on a buried oxide layer. The gate region of this invention includes a gate electrode and a field plate extending laterally from the gate electrode over the lateral linear doping region.

Method for making an improved high voltage thin film transistor having a

The present application is directed to an improved arrangement for a thin silicon SOI transistor having improved source-high performance especially for bridge type circuits. This structure prevents forward current saturation during such source-high operations, and is made by forming the laterally extending silicon layer with a region of thinner thickness over 1/3 to 2/3 of the length of the drift region, or the lateral linear doping region. The field plate is formed with a separation from the gate electrode, and only extends over the thinned portion of the drift region. The gate electrode and field plate are short-circuited by a metal interconnect.

SOI transistor with improved source-high performance

The present invention is directed to a method and thin film transistor having a linear doping profile between the gate and drain regions. This is constructed in a particular manner in order to achieve a thin film transistor having a significantly high breakdown voltage of the order of 700 to 900 volts, much greater than that achieved in the prior art.

High voltage thin film transistor having a linear doping profile and

An improvement in a self-passivated high voltage semiconductor device is set forth with a thinned SOI layer having a linear lateral doping region coated with an oxide layer and a field plate being a part of the gate electrode layer. A high voltage SOI semiconductor device is formed having freedom from external electric fields.

A very thin silicon film SOI device can be made utilizing a bond and etch-back process. In the presently claimed invention, boron dopant is introduced into a surface of a silicon device wafer and the doped surface is bonded onto another silicon wafer at an oxide surface. The device wafer is thinned by etching down to the doped region and, by subsequent annealing in hydrogen, boron is diffused out of the silicon surface layer to produce very thin SOI films.

Process for making thin film silicon-on-insulator wafers employing wafer

A silicon on insulator of integrated circuit comprising a plurality of components typically adopted for high voltage application having a semiconductor substrate of a first conductivity type, an insulating layer provided on the substrate, a semiconductor layer provided on the insulating layer, a number of laterally separated circuit elements forming parts of a number of subcircuits provided in the semiconductor layer, a diffusion layer of a second conductivity type opposite to that of the first conductivity type provided in the substrate and laterally separated from all the other circuit elements and means for holding the diffusion layer at a voltage at least equal to that of the highest potential of any of the subcircuits present in the integrated device.

Growing community of inventors

Phoenix, AZ, United States of America

Steven L Merchant