Spectralink Corporation

Steven L Maddy

Graeme S Paterson

A portion of a FSK signal is encoded with a central frequency (f.sub.0) and the FSK signal is transmitted. A receiver captures the transmitted FSK signal, and demodulates the FSK signal to provide and analog data signal. The analog data signal is DC coupled to a first input of a comparator. The comparator generates a logic level binary output corresponding to the FSK signal. A second input of the comparator is coupled to a bias circuit. Preferably the bias circuit is provided by a digital to analog convertor (DAC). A control circuit detects the predetermined portion of the FSK signal in which the center of frequency is being transmitted. During the predetermined portion the control circuit samples the binary logic level output of the comparator, converts the binary logic level output to a digital error word, and uses the digital error word to control the DAC.

Apparatus and method for automatic discriminator compensation in a FSK

A phase locked loop including a switch between a phase detector output and a VCO input to open the PLL during a frequency change is provided. While the PLL is open, an analog error correction signal is generated by sampling any residual error coming from the phase detector, and generating the analog error correction signal to counter the residual error. Once analog error correction signal is available, the switch is closed and the error correction signal is added to the phase detector output and the PLL is allowed to settle to an optimized frequency.

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Boulder, CO, United States of America

Steven L Maddy