Polar Semiconductor, Inc.

Allegro Microsystems, LLC

Sanken Electric Co., Ltd.

Polarfab, LLC

Steven L Kosier

Peter West

Don Rankila

Tatsuya Kamimura

Noel P Hoilien

Shunsuke Fukunaga

David G Erie

Gregory Delmain

Dosi Dosev

Joseph Burkhardt

Thomas S Chung

Peter Nicholas Manos

Kurt Kimber

David Litfin

Noel Hoillien

David M Elwood

Ronald Harlan

A trench semiconductor device includes a layer of semiconductor material, an exterior trench pattern formed in the layer of semiconductor material, and an interior trench pattern formed in the layer of semiconductor material, at least partially surrounded by the exterior trench pattern. The exterior trench pattern includes a plurality of exterior trench portions that are each lined with dielectric material and filled with conductive material, and the interior trench pattern includes a plurality of interior trench portions that are each lined with dielectric material and filled with conductive material.

Trench semiconductor device layout configurations

A structure having collocated magnetic field sensing elements can be used to simultaneously determine magnetic field and mechanical stress. A primary magnetic field sensing element generates a primary signal responsive to a magnetic field and a secondary magnetic field sensing element generates a secondary signal responsive to mechanical stress. A system includes a stress compensation module to receive the primary and signals, and to compensate for mechanical stress in the primary signal.

Structure and system for simultaneous sensing a magnetic field and mechanical stress

Apparatus and associated methods relate to controlling an electric field profile within a drift region of an LDMOS device using first and second RESURF regions. The first RESURF region extends from a source end toward a drain end of the LDMOS device. The first RESURF region is adjacent to a forms a metallurgical junction with the drift region. The second RESURF layer extends from the drain end toward the source end of the LDMOS device. The second RESURF layer has an end that is longitudinally between the body contact and the source end of the first RESURF layer. A distance between the end of the second RESURF layer and the body contact is greater than a vertical distance between the end of the second RESURF layer and the body contact. A maximum electric field between the second RESURF layer and the body contact can be advantageously reduced with this geometry.

LDMOS transistor with lightly-doped annular RESURF periphery

Apparatus and associated methods relate to controlling an electric field profile within a drift region of an LDMOS device using biased field plates to deplete majority carriers from a drift region between a body/drift-region metallurgical junction and a drain contact. Such field plates are located in trenches that longitudinally extend within the drift region. Field plates are laterally spaced apart from each other at a distance that permits substantial depletion of majority carriers between adjacent field plates. Trenches have trench bottoms located within a drift-region/substrate metallurgical junction so as to permit substantial depletion of majority carriers between trench bottoms and the drift-region/substrate metallurgical junction. Between adjacent trenches, dopant concentrations can be increased up to a threshold that can be substantially depleted under specified bias conditions. Such control of the electric field profile within the drift region may advantageously optimize a breakdown-voltage/on-resistance characteristic of the LDMOS device.

Drift-region field control of an LDMOS transistor using biased shallow-trench field plates

Apparatus and associated methods relate to a bonding pad structure for a trench-based semiconductor device. The bonding pad structure reduces a peak magnitude of the electric field between a metal bonding pad and the underlying semiconductor. The bonding pad structure includes a plurality of trenches vertically extending from a top surface of a semiconductor. Each of the plurality of trenches has dielectric sidewalls and a dielectric bottom, the dielectric sidewalls and dielectric bottom electrically isolating a conductive core within each of the trenches from a region of semiconductor outside of and adjacent to each of the plurality of trenches. The bonding pad structure includes a metal bonding pad disposed above the plurality of trenches, the metal bonding pad electrically isolated from the region of semiconductor outside of the trenches. The conductive core can be biased to reduce the magnitude of the field between adjacent trenches.

High voltage tolerant bonding pad structure for trench-based semiconductor devices

Apparatus and associated methods relate to an edge-termination structure surrounding a high-voltage MOSFET for reducing a peak lateral electric field. The edge-termination structure includes a sequence of annular trenches and semiconductor pillars circumscribing the high-voltage MOSFET. Each of the annular trenches is laterally separated from the other annular trenches by one of the semiconductor pillars. Each of the annular trenches has dielectric sidewalls and a dielectric bottom electrically isolating a conductive core within each of the annular trenches from a drain-biased region of the semiconductor pillar outside of and adjacent to the annular trench. The conductive core of the innermost trench is biased, while the conductive cores of one or more outer trenches are floating. In some embodiments, a surface of an inner semiconductor pillar is biased as well. The peak lateral electric field can advantageously be reduced by physical arrangement of trenches and electrical biasing sequence.

Termination trench structures for high-voltage split-gate MOS devices

In one aspect, a vertical Hall effect sensor includes a semiconductor wafer having a first conductivity type and a plurality of semiconductive electrodes disposed on the semiconductor wafer. The plurality of semiconductive electrodes have the first conductivity type and include a source electrode, a first sensing electrode and a second sensing electrode, arranged such that the source electrode is between the first sensing electrode and the sensing electrode and a first drain electrode and a second drain electrode, arranged such that the first sensing electrode, second sensing electrode, and source electrode are between the first drain electrode and the second drain electrode. The vertical Hall effect sensor also includes a plurality of semiconductor fingers disposed on the semiconductor wafer and interdigitated with the plurality of semiconductive electrodes, the semiconductor fingers having a second conductivity type.

Vertical hall effect sensor

Novel anisotropic magneto-resistive (AMR) sensor architectures and techniques for fabricating same are described. In at least one embodiment, an AMR sensor is provided that includes barber pole structures having upper and low metal layers that are formed of different materials. The metal material closer to the AMR element is formed of a material that can be etched using an etching process that does not attack the AMR material. In some other embodiments, AMR sensors having segmented AMR sensing elements are described.

Anisotropic magnetoresistive (AMR) sensors and techniques for fabricating same

A Hall effect transducer in a semiconductor wafer comprises a first layer of semiconducting material, a second layer of semiconducting material, and a contact structure configured to provide a path for electrical current to pass through the second layer. The second layer has higher electron hole mobility than the first layer, and is epitaxially grown atop the first layer.

Integrated hybrid hall effect transducer

A diode conducts current between an anode terminal and a cathode terminal. The diode includes a parasitic transistor formed between one of the terminals and the substrate. The diode also includes a second transistor that competes with the parasitic transistor to direct current flow between the anode terminal and the cathode terminal.

Diode structure to suppress parasitic current

An antifuse device is constructed from a bipolar junction transistor (BJT). The BJT includes a collector, a base, and an emitter. In one embodiment the BJT is formed inherently within a field effect transistor (FET), including a first doped region, a second doped region, a gate, and a body region. The collector of the BJT is realized by the first doped region of the FET, the emitter of the BJT is realized by the second doped region of the FET, and the base of the BJT is realized by the body region. A high resistance path exists between the collector and the base. A first input voltage is connected to the collector and a second input voltage is connected to the base. A switch connects the emitter to a fixed potential when the switch is closed. The antifuse device is programmed by closing the switch and allowing the first input voltage and the second input voltage to create a large current from the collector to the emitter, through the base, such that the high resistance path between the collector and the base is converted to a permanent low resistance path.

Bipolar junction transistor antifuse

A method to create a layout of a semiconductor device for the purpose of fabricating the semiconductor device involves first providing a plurality of partial-area layout cells and then generating the layout of the semiconductor device by placing the plurality of the partial-area layout cells together. The layout can be conveniently expanded to a desirable size by replicating or repeating certain repeatable cells.

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Lakeville, MN, United States of America

Steven L Kosier