National Semiconductor Corporation

Texas Instruments Corporation

Steven L Harris

Steven Michael Barrow

Robert Oppen

Robert Henry Bell

W David Pace

A method includes generating a drive signal for a transistor in a switching regulator. The drive signal turns the transistor on and off to generate a regulated output voltage. The drive signal is generated based on a clock signal. The method also includes dynamically decreasing a frequency of the clock signal to decrease a dropout voltage of the switching regulator. Dynamically decreasing the frequency of the clock signal can increase a duration of switching periods defined by the clock signal. The dropout voltage could have a first value proportional to T/Tduring shorter switching periods and a second value proportional to T/Tduring longer switching periods. Trepresents a minimum amount of off-time for the transistor during each switching period, Trepresents a maximum amount of on-time for the transistor during shorter switching periods, and Trepresent a maximum amount of on-time for the transistor during longer switching periods.

Buck regulators with adjustable clock frequency to achieve dropout voltage reduction

Two comparators are arranged to generate a pulse-width modulator (PWM) control pulse. The first comparator is arranged to start the PWM control pulse, while the second comparator is arranged to stop the PWM control pulse. The first comparator can be a high speed CMOS comparator that includes a built-in offset. The first and second comparators can be arranged such that the built-in offset of the first comparator dominates the overall operation at the start of the control pulse. The start of the PWM control pulse is initiated by a ramp voltage and a predetermined reference level instead of a clock edge. The PWM control pulse can be linearly varied down to a zero pulse width. The PWM control pulse may be used to control the on-time of the switching element in a switching-type converter.

Two comparator voltage mode PWM

The on-time of a pulse signal is controlled by comparing a ramp signal to an input signal that is dynamically selected from two signals. A first operating mode is active when a clock signal is in a first logic state, where the pulse signal is reset. A second operating mode is initiated when the clock signal changes from the first logic state to a second logic state. During the second operating mode, the ramp signal is compared to the first signal. A third operating mode is initiated when the ramp signal exceeds the first signal during the second operating mode. During the third operating mode, the pulse signal is set and the ramp signal is compared to the second signal. The pulse signal is reset when the when the ramp signal exceeds the second signal in the third operating mode such that the on-time of the pulse signal is controlled.

Growing community of inventors

Chandler, AZ, United States of America

Steven L Harris