General Electric Company

Yokogawa Electric Corporation

Yokogawa Elect. Corp.

Steven L Garverick

Kenji Fujino

Donald Thomas McGrath

Joseph E Krisciunas

Jerome Johnson Tiemann

Matthew N O'Donnell

Gerald J Michon

Sharbel E Noujaim

Fathy F Yassa

Philippe L Jacob

Masaaki Nishijo

Masami Imamoto

A monolithic integrated circuit as may be used in combination with a plurality of sensors for generating respective sensor output signals, which monolithic integrated circuit includes means for converting each sensor output signal to bit-serial digital format, together with some initial processing circuitry comprising a bit-serial multiply-add processor. This processor includes a bit-serial digital multiplier for multiplying a first digital processor input signal in bit-serial form by a second digital processor input signal to generate a digital product signal, a digital adder for adding a third digital processor input signal to the digital product signal to generate a digital sum signal, and means for supplying a digital processor output signal with bits correspond-ing to those of said digital sum signal. A memory system provides memory for storing program instructions, memory for storing successive values of the second digital processor input signal, memory for storing successive values of the third digital processor input signal, and memory for storing successive values of the digital processor output signal as written into the memory system. The first digital processor input signal can be selected from among the sensor output signals as converted to bit-serial digital format. The second digital processor input signals applied to the bit-serial multiply-add processor are at least at selected times read from the memory system, as are the third digital processor input signals applied to the bit-serial multiply-add processor. A controller retrieves stored program instructions in a prescribed order from the memory for storing program instructions and generates control signals for controlling at least the reading and writing of the memory system, as well as the selecting of the first digital processor input signal.

Analog voltage metering system with programmable bit-serial digital

A programmable length decimation filter responsive to an externally derived stream of quantized electrical signals arriving at a predetermined rate comprises a counter, a resolution filter, and an accumulator. The resolution filter is responsive to the counter output signals, to an externally derived resolution select signal, and to the stream of quantized signals, and operates to mask selected quantized signals in order to provide resolution filter output signals to the accumulator on a plurality of resolution filter output ports. The resolution select signal allows for providing flexibility of operation regarding the tradeoff of the bandwidth of the decimation filter with its resolution capability.

Programmable length decimation filter as for sigma-delta modulators

An output circuit for use with an array of analog energy detectors includes a system for digital companding which is capable of providing output signals with an enhanced dynamic range. A digital compressor is provided for converting the output signals of the analog detectors into compressed digital values. Accumulators are provided for holding the output signals of the digital compressor. An expander is provided to expand the digital output signals held in the accumulators to determine the energy patterns impinging on the array of analog detectors.

Architecture for arbitrary nonlinear quantization of multi-channel data

Data acquisition systems with programmable bit-serial digital signal

A system for processing digital electrical power signals derived from at least one externally supplied, substantially continuous, substantially alternating, electrical signal having a primary or fundamental frequency, comprises: a multiply-accumulate arithmetic processor having three input ports with at least one input port for receiving the digital electrical power signals, an output port and a processor control port; a first memory unit for storing a plurality of processor control signals; a second and third memory unit each for storing a separate plurality of processor input signals; and a memory control unit having the capability to respectively couple the first memory unit to the processor control port, and the first processor input port to one of the second and third memory units for each cycle of the primary frequency so that newly received digital electrical power signals may be continually processed by the processor for a predetermined number of cycles.

Programmable digital signal processor system for processing electrical

A method for measuring at least one electrical parameter of the operation of a p-phase power line, p being a positive integer, arranges respective sensing apparatus to sense at least one of the voltages and currents associated with each phase of the power line. Analog-to-digital conversion apparatus is used to digitize the response of each sensing apparatus, thereby to generate corresponding digital responses. A digital computer is used to correct each digitized response of the analog-to-digital conversion apparatus for non-linearities, gain errors and phasing errors in the responses of the sensing apparatus and for non-linearities and gain errors in the responses of the analog-to-digital conversion apparatus. The computer is used to high-pass digitally filter each digital response that has been corrected, in order to suppress any attendant direct term. The digital computer then calculates each the electrical parameter, proceeding from each digital response that has been corrected and has been high-pass digitally filtered.

Measuring electrical parameters of power line operation, using a digital

A decimation filter in which two filtering processes are carried out on a time-division-multiplexed basis using kernels that are sampled-data representations of triangular waves, one of which triangular waves decrements while the other increments, or vice versa. A digital multiplier receives the time-interleaved kernels as a multiplicand and receives as a multiplier a stream of bits supplied at a rate that is one-quarter that of the filter clock pulses. The digital multiplier applies its product output signal to the addend input port of a parallel-bit adder. The sum output port of this adder connects to a cascade connection of first, second, third and fourth clocked latches. The signal from the output port of the fourth clocked latch is supplied to the augend input port of the adder except during the first four clock pulse durations after the kernel values reach maxima. The signal from the output port of the third clocked latch is supplied to the augend input port of the adder during zeroeth and second clock pulse durations after the kernel values reach maxima, and arithmetic zero is supplied to the augend input port of the adder during the first and third clock pulse durations after the kernel values reach maxima. First and second output signals for the decimation filter are extracted from the output ports of the second and fourth clocked latches. This decimation filter can be used on a single-channel or dual-channel basis.

Plural-channel decimation filter, as for sigma-delta analog-to-digital

A beam former in a PASS ultrasonic imaging system includes a set of sigma-delta modulators which operate to separately digitize the received echo signal from each transducer element. The oversampled one-bit digital representations of each echo signal are delayed as required for beam steering and focusing, and are summed together. A decimator filter reduces the sample rate of the digitized receive beam prior to display of the image resulting from the receive beam.

Phased array ultrasonic beam forming using oversampled A/D converters

A delta sigma analog-to-digital (A/D) converter includes a digitally-controlled multiplying digital-to-analog converter (MDAC) in a feedback configuration. The MDAC is driven by a digital signal obtained from the output (or an intermediate output) of the A/D converter. An incremental feedback quantum to the first stage integrator is a function of the input values that immediately precede it. In the most general implementation, a table look-up permits an arbitrary relation between the input values and feedback quantum size. In another implementation, the A/D converter output (or intermediate output) signal drive the MDAC and the compression curve of the A/D converter bears a square-root relationship to the input analog signal; a linear relationship is restored by squaring the output signal. In a third implementation, the MDAC is driven by a digital signal obtained from the output (or an intermediate output) of the A/D converter together with an added small positive constant number. In this implementation, the compression curve starts out approximately linear and approaches a square-root relationship at the high end of the scale, while a linear relationship is restored by providing the feedback loop, in the digital domain, with the same value of signal as employed in the analog domain.

Delta sigma analog-to-digital converter with increased dynamic range

An oversampled interpolative delta sigma analog-to-digital converter including a delta sigma modulator is provided with a cascade of bit-slice elements at the output of the modulator to form a filter/decimator. Each bit-slice element includes a filter circuit that filters the bit-rate signal in accordance with an arbitrary filter impulse response input signal to provide the converter with a filter characteristic that can be controllably varied without modifying the filter hardware. In each bit-slice element, an adder circuit and a delay circuit decimate the bit-rate signal produced by the delta sigma modulator to provide a digital output signal at a clock cycle rate equal to the Nyquist rate. The filter/decimator also provides encoding of the delta sigma output in 2's complement format.

Digital filter for filtering and decimating delta sigma modulator output

A bit-serial processor for selectively carrying out the sequential steps of performing by successive approximations Coordinate Rotation Digital Computation (CORDIC), non-restoring division or non-restoring square rooting calculations is suitable for inclusion in a monolithic integrated circuit with a plurality of sensors for generating respective sensor output signals, circuitry for converting each sensor output signal to bit-serial digital format, and a bit-serial muliptly-add processor. Together with an electrically-erasable programmable read-only memory and a plurality of current transformers, the monolithic integrated circuit implements a system for metering a-c power main conductors.

Digital signal processor for selectively performing cordic, division or

A decimation filter in which two filtering processes are carried out on a time-division-multiplexed basis using kernels that are sampled-data representations of triangular waves, one of which waves decrements while the other increments, or vice versa. A digital multiplier is connected for receiving the time interleaved kernels and a stream of bits supplied at a rate that is one-quarter of which the filter clock pulses regularly recur. The multiplier's output is connected to the addend input of a parallel-bit adder. The adder's output is connected to a cascade connection of first, second, third and fourth clocked latches. The output signal of the fourth latch is supplied to the adder's augend input except during the first four clock pulse durations after the kernel values reach maxima. The output signal of the third latch is supplied to the adder's augend input during zeroeth and second clock pulse durations after the kernel values reach maxima, and arithmetic zero is supplied to the adder's augend input during the first and third clock pulse durations after the kernel values reach maxima. The filter's first and second output signals are extracted from the outputs of the second and fourth latches. This filter can be used on a single-channel basis. Alternatively, this filter is used on a dual-channel basis with a two-input multiplexer supplying the stream of bits to one of the multiplier's inputs. Also, plural of these filters can be joined to provide multiple-channel decimation filtering.

A differential delta-sigma modulator of switched-capacitance type is operated with a three-phase cycle, rather than the two-phase cycle of the prior art. In the first phase of operation the switched capacitors are charged in accordance with the previous single-bit output of the modulator. Structural modifications permit the switching capacitors to be connected in series to receive the modulator input voltage during the second phase of operation so that voltage need not be balanced with regard to any specified common-mode potential. In the third phase of operation the switched capacitors discharge from first plates thereof to the differential-input integrator while the second plates thereof are driven in accordance with the previous single-bit output of the modulator.

Growing community of inventors

Schenectady, NY, United States of America

Steven L Garverick