Other

Stratus Computer, Inc.

Steven Kohalmi

Walter Clark Milliken

Philip P Carvey

Craig Partridge

Ronald L Pettyjohn

Gregory M Green

Stanley P Sassower

Karen R Bricknell

A computer system for transmitting packets includes a manager and scheduling elements for managing the transmission of the packets over one or more logical channels. The computer system can prioritize the transmission of packets based on the type of traffic and maintain quality of service (QoS) characteristics associated with a logical channel. In addition, the computer system can execute a threading process to ensure the efficient and timely transmission of certain types of packets without using any complex mathematical operations.

System and method for scheduling and rescheduling the transmission of cell objects of different traffic types

A method for managing the transmission of packet objects distinguishes between packet objects having and not having quality of service (QoS) requirements for transmission over a logical channel. Packet objects for a logical channel having QoS requirements are placed in a sorted tree queue based on its scheduled departure time and on a weighting system related to the QoS requirements. Packet objects for a logical channel only requiring best effort transmission are place in a FIFO queue. Each logical channel is associated with either a sorted tree queue or a FIFO queue.

System and method for scheduling the transmission of packet objects having quality of service requirements

A novel mapping and protection circuit arrangement comprises a plurality of checking mechanisms that collectively cooperate to verify the accuracy of I/O addresses generated by input/output (I/O) controllers of a fault-tolerant computer. These verified I/O addresses are translated into system addresses to enable direct memory access (DMA) transactions between the controllers and the computer's host memory. Specifically, certain of the checking mechanisms cooperate to ensure that the DMA accesses are directed to correct pages in host memory, while other checking mechanisms are provided to ensure that memory access operations are performed at correct locations within the page. Additional checking mechanisms are provided to further verify the accuracy of generated I/O addresses.

Method and apparatus for validating I/O addresses in a fault-tolerant

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Newton, MA, United States of America

Steven Kohalmi