Zilog, Inc.

Ixys Ch Gmbh

Ubicom Gmbh

Steven K Fong

A clock input filter uses a first programmable low-pass delay element to filter during a low period of an input clock signal and to output a SET signal. The clock input filter uses a second programmable low-pass delay element to filter during a high period of the input clock signal and to output a RESET signal. A latch is set and reset by the SET and RESET signals. The latch outputs a filtered version of the input signal that has the same approximate duty cycle as the input signal. A pair of gates generates a corresponding pair of duty cycle adjusted versions of the input signal. Output multiplexing circuitry is provided to output either the output of the latch, or an increased duty cycle version of the input signal, or a decreased duty cycle version of the input signal, or an unfiltered version of the input signal.

Clock input filter circuit

A circuit with reduced short current. A first pair of delay transistors separates a second pair of transistors and prevents short current from flowing through the second pair of transistors.

Growing community of inventors

Saratoga, CA, United States of America

Steven K Fong