International Business Machines Corporation

Kyndryl, Inc.

Steven Joseph Kurtz

Ronald Dennis Rose

David J Widiger

Mark Alan Lavin

Vladimir P Zolotov

Lewis William Dewey, Iii

Sanjay Upreti

Susan Elizabeth Cellier

Richard W Taggart

John Atkinson Fifield

Clea Anne Zolotow

Tedrick Neal Northway

Pritpal Arora

Laxmikantha Sai Nanduru

Computer systems that use artificial intelligence to predict strategies, scenarios and or game plans for sports games that are already in progress. In some embodiments a feedback loop is used so that the artificial intelligence takes into account events occurring in and/or around the game as they occur to provide updated predictions.

Artificial intelligence assisted sports strategy predictor

An effective spacing is calculated for each physical spacing between two or more neighbor nets of a target net. Segment boundaries are determined based on the calculated effective spacing to define segments for the target net and one of the segments is selected. A metal configuration for the selected segment is identified and a table of capacitance per-unit-length is accessed for the identified metal configuration to return an above capacitance value, a below capacitance value, a left-side capacitance value, and a right-side capacitance value for the corresponding segment, the table comprising at least a two-dimensional (2D) table. The capacitance values are scaled based on a corresponding segment length determined from the calculated effective spacing. The selecting, identifying, accessing and scaling operations are repeated for each remaining segment of the target net. Optionally, the above, below, left, and right capacitance values for all segments of the target net are summed.

Capacitance extraction

An integrated circuit includes a target wiring layer, a first adjacent wiring layer above the target wiring layer, and a second adjacent wiring layer below the target wiring layer. Each adjacent wiring layer including crossing wires orthogonal to the target wiring layer. Modify a putative design of the integrated circuit by selecting a target wire; identifying lateral neighbors of the target wire; defining regions of the target wire where the lateral neighbors are homogeneous in cross-section; for each region of the target wire, calculating a wire pattern for the crossing wires; identifying segments within above and below portions of the wire pattern; for each above and below segment pair, obtaining a per-unit-length capacitance from a reduced pattern database; extracting a total parasitic capacitance from the per-unit-length pattern capacitances; and in response to an assessment of the impact of the total parasitic capacitance on circuit performance, producing a modified design.

Extracting parasitic capacitance from circuit designs

A computer-implemented method includes identifying a noise cluster, representing the noise cluster according to a variational model, projecting the variational model onto one or more corners to yield a projected noise cluster, and determining a computed noise for the projected noise cluster. Optionally, the noise cluster includes one or more noise cluster elements, and each of the noise cluster elements are expressed as one or more circuit element terms, according to a canonical form. Optionally, at least one of the corners is a bounding corner. For the bounding corner, the projected noise cluster is generated by maximizing the circuit element terms for those noise cluster elements that tend to increase noise, and by minimizing the circuit element terms for those noise cluster elements that tend to decrease noise, whereby noise is maximized for the canonical form. A corresponding computer program product and computer system are also disclosed.

Analysis of coupled noise for integrated circuit design

The accuracy of electronic design automation is increased by determining whether fill wires in a putative integrated circuit design should be effectively grounded or floating. For each signal wire in the putative design adjacent to the fill wires, a signal sensitivity value, which represents sensitivity of a given one of the plurality of signal wires to noise and timing, is determined. For each one of the fill wires, a fill sensitivity value is determined by: identifying coupling of each one of the fill wires to the adjacent signal wires; and calculating the fill sensitivity value as a combination of the signal sensitivity values of each of the adjacent signal wires for which the coupling has been identified. At least a portion of the fill wires are selectively effectively grounded based on the fill sensitivity value, to obtain a modified design.

Selectively grounding fill wires

A method for predicting noise propagation in a circuit comprising correlating noise results predicted by a circuit model to a transistor level model with a processor, generating a first best fit data analytics model for identifying the optimal output pin capacitance as a function of circuit conditions and store the first best fit model in a noise rule file in a memory, generating a second best fit data analytics model for predicting noise peak output from the circuit model as a function of the circuit conditions and store the second best fit model in the noise rule file in the memory, and applying the first best fit model and the second best fit model in a noise analysis simulation to identify and simulate an optimal circuit.

Predicting noise propagation in circuits

A nano-magnetic element array having a conductive line adjacent to a group of nano-magnetic elements and a multi-level current driver connected to an input node on the conductive line. The current driver is controlled by a pair of voltage clock signals and a voltage reference so as to selectively change the current amount at the input node between a first level that erases the state of the elements, a second level that switches the state of the elements and a third level that maintains the state of the elements. The current driver is further configured so that the transition from the second to the third level is gradual. Optionally, a bias generator can selectively adjust the voltage reference and thereby, the current amount at the input node. Also, optionally, the same voltage clock signal and voltage reference lines can be used to control multiple multi-level current drivers within the array.

Growing community of inventors

Austin, TX, United States of America

Steven Joseph Kurtz