International Business Machines Corporation

Jds Uniphase Corporation

Globalfoundries Inc.

Steven John Baumgartner

David W Siljenberg

Charles Porter Geer

Dana Marie Woeste

Daniel Mark Dreps

Anthony Richard Bonaccio

Timothy Clyde Buchholtz

Matthew James Paschal

Patrick Lee Rosno

Michael B Spear

David Paul Paulsen

Anthony Gus Aipperspach

Sergey Vladimirovich Rylov

Mounir Meghelli

Stephen J Ames

Alan P Wagstaff

Daniel Guy Young

Daniel Scott Hedin

Hayden C Cranford, Jr

Frank David Ferraiolo

John Francis Bulzacchelli

Andrew Benson Maki

James Johnson

Michael Anthony Sorna

Thomas W Liang

Clint Lee Schow

Salvatore Nicholas Storino

Joseph Natonio

Andrew Douglas Davies

Susan M Eickhoff

Rick Allen Philpott

Steven John Zier

David M Onsongo

Kevin Paul Demsky

Raymond J Thatcher

Steven Elliott Mikes

Christopher Keith White

Chun-Tao Li

Brad Anthony Natzke

Kenneth Paul Jackson

William D Corti

John K Koehler

Mankit Wong

Anh Duy Ngo

Thomas Pham

Disclosed is a linear feedback shift register (LFSR)-based clock signal generator that includes an LFSR, which outputs multi-bit states based on a system clock signal (CLK). Based on the multi-bit states, a single-phase pulse generator generates first and second clock signals (CLKand CLK), where the pulse rate of CLKis slower than that of the CLKand greater than that of CLK. In some embodiments, a first multi-phase pulse generator can generate N-phases of the CLKbased on CLKand N-phases of the CLKand a second multi-phase pulse generator can generate N-phases of CLKbased on CLKand N-phases of CLK. Furthermore, additional registers can optionally use the N-phases of CLKto further generate N sets of M-phases of the CLK. Also disclosed are a multi-level circuit (e.g., a time domain-interleaved analog-to-digital converter (ADC)), which incorporates the LFSR-based clock signal generator, and associated methods.

Linear feedback shift register-based clock signal generator, time domain-interleaved analog to digital converter and methods

A digital data communications mechanism includes multiple parallel lines, in which components of one or more lines are temporarily powered down to save power. Preferably, both the transmitter and receiver contain respective generators generating identical pre-determined pseudo-random bit streams, which are initially synchronized and which remain powered up when the line is temporarily powered down. Upon re-powering the line, the transmitter transmits the locally generated bit stream, and the receiver compares the received bit stream with its internally generated bit stream to determine an amount of shift required for re-synchronization.

Power reduction in a parallel data communications interface using clock resynchronization

A computer-implemented method includes receiving layout information associated with a circuit design at an extractor, and generating three-dimensional (3-D) heat source grid information based on the layout information, an extracted netlist, and wire information. The method also includes sending the wire information to an electromigration(EM)/current(IR) analyzer, sending the extracted netlist to a circuit simulator, and sending the 3-D heat source grid information to a thermal analysis component. The circuit simulator is configured to generate temperature waveforms and current waveforms based on the extracted netlist. The thermal analysis component is configured to generate heat source information to be provided to the EM/IR analyzer. The method further includes determining, at the EM/IR analyzer, an electromigration risk associated with a wire based on the wire information, the current waveforms, and the heat source information.

Heat source integration for electromigration analysis

A level-shifting latch circuit for coupling a first circuit in a first voltage domain with a second circuit in a second voltage domain, includes an input node to receive an input signal provided by the first circuit, and an output node to output a level-shifted signal, corresponding with the input signal. The level-shifting latch circuit also includes a first latch, having a first node and a second node, for storing the input signal in the first voltage domain, and a second latch, having a third node and a fourth node, for storing the input signal in the second voltage domain. In addition, the level-shifting circuit also includes a first switching element which provides a path to transfer a low voltage at the first node to the third node, and a second switching element which provides a path to transfer a low voltage at the second node to the fourth node.

Level-shifting latch

A communications link includes multiple continuously calibrated parallel lines, wherein one or more lines are at least partially powered down while being continuously calibrated to reduce power consumption. In one aspect, at least N+1 lines (where N is the logical bus width) are periodically recalibrated, and at least one redundant line is powered down between calibrations. The redundant line could be either a true spare available for use as a replacement, or an extra line which carries functional data while other lines are being calibrated in turn. In another aspect, the logical bus width is variable, but does not exceed N. When N&#x3c;N, lines not carrying functional data are partially powered down between calibrations.

Parallel data communications mechanism having reduced power continuously calibrated lines

A system and method for testing digital to analog converters (DAC) in a serial interface having a comparator to receive an input signal and a local offset signal is disclosed. A first DAC selectably provides one of a global offset to the input signal during a normal mode of operation and a first test signal to the comparator during a test mode of operation. A second DAC selectably provides one of the local offset signals to the comparator during the normal mode of operation and a second test signal to the comparator during the test mode of operation. A test module may cause the first DAC to determine a first test signal to provide to the local offset input of the comparator and may cause the second DAC to incrementally change a test signal provided to the comparator.

Testing of digital to analog converters in serial interfaces

A design structure embodied in a machine readable medium used in a design process includes a current mirror circuit that includes a reference current source that generates a reference current, a reference transistor, a mirror transistor and a ratioed body bias feedback unit. The reference transistor has a first node that is coupled to the output of the reference current source, a gate that is coupled to the first node and a second node coupled to a common voltage. The mirror transistor has a gate coupled to the first node. The ratioed body bias feedback unit generates a body bias voltage coupled to the body of the reference transistor and the body of the mirror transistor. The ratioed body bias feedback unit is configured to adjust the body bias voltage in relationship to the common voltage so that the reference transistor and the mirror transistor each have a threshold voltage within a predefined range.

Ratioed feedback body voltage bias generator

A design structure for a high speed computer processor system includes a high speed interface for a graphics processor. In a preferred embodiment, the high speed interface includes a front side bus (FSB) that interfaces to a similar high speed interface on the graphics processor.

Architecture for a physical interface of a high speed front side bus

A phase locked loop generates an output corresponding to a source synchronous input and an input link clock signal. A phase locking feedback system receives the input and an input link clock signal and detects phase deviations between the output and the input. The phase locking feedback system also adjusts an adjusted clock signal based on the phase deviations thereby causing the phase locking feedback system to generate the output so that the output has a steady phase relationship with the input. A first mechanism causes the phase locking feedback system not to track phase deviations between the output and the input upon occurrence of a first predefined event, thereby maintaining the adjusted clock signal at a current state.

Unlock mode in source synchronous receivers

A design structure is described for dynamically aligning clocks in independent clock domains with minimal latency. In the preferred embodiments, a reference clock in the destination clock domain that is some multiple times the data clock of the destination clock domain is used to sample a data sample signal from the source domain. The sampled data is used to determine at what time slice of the reference clock the data sample signal is changing and therefore at what phase of time slice or phase of the data clock the clocks can be aligned to ensure valid data will be transferred between clock domains.

Dynamic clock phase alignment between independent clock domains

An apparatus and method is provided for sensing which faults have occurred in a laser control system, as well as trapping and identifying the first fault occurrence. The apparatus includes an integrated circuit in which a mask register is set by means of a micro-controller or a host system to select which fault sources are to be recorded. A status bit register in which the fault indications are stored can also be interrogated by the micro-controller or a host system. A settable first fault status register determines whether every fault or only the first fault gets recorded.

Fault sensor for a laser driver circuit

A method for implementing phase rotator circuits and phase rotator circuit of the invention includes a polyphase filter network to create a quadrature phase version of the input signal. The polyphase filter network is partitioned into a first part that is physically isolated from the phase rotator circuit and a second part that is embedded in the phase rotator circuit. The second part of the polyphase filter is coupled to the first part of the polyphase filter by a high-pass equalizing buffer stage. The second part of the polyphase filter is coupled to the phase rotator circuit by a bandlimiting buffer stage.

Implementing phase rotator circuits with embedded polyphase filter network stage

An apparatus and method is described for dynamically aligning clocks in independent clock domains with minimal latency. In the preferred embodiments, a reference clock in the destination clock domain that is some multiple times the data clock of the destination clock domain is used to sample a data sample signal from the source domain. The sampled data is used to determine at what time slice of the reference clock the data sample signal is changing and therefore at what phase of time slice or phase of the data clock the clocks can be aligned to ensure valid data will be transferred between clock domains.

Growing community of inventors

Zumbro Falls, MN, United States of America

Steven John Baumgartner