International Business Machines Corporation

Steven Jay Munroe

Erik Edward Voldal

Steven Lester Halter

Scott N Gerard

John Clarence Endicott

Michael K Gschwind

Robert Peter Resch

Robert J Blainey

James Lawrence McInnes

James William Stopyro

John Gerard Nistler

William Jon Schmidt

Xin Xu

Jin Song Ji

Ronald Ian McIntosh

David Charles Boutcher

Jeffrey Jay Scheel

Raymond Keith Harney

Maynard Paul Johnson

Michael R Meissner

Michael Dennis McKeehan

Ashok Malhotra

Vincent Joseph Kruskal

Scott Alan Plaetzer

James Gregory Ranweiler

George D Timms, Jr

Robert Eugene Westland

Anthony Edward Brock

Abolfazi Sirjani

An optimizing compiler includes a vector optimization mechanism that optimizes vector instructions by eliminating one or more vector element reverse operations. The compiler can generate code that includes multiple vector element reverse operations that are inserted by the compiler to account for a mismatch between the endian bias of the instruction and the endian preference indicated by the programmer or programming environment. The compiler then analyzes the code and reduces the number of vector element reverse operations to improve the run-time performance of the code.

Compiler optimizations for vector instructions

Generating decode time instruction optimization (DTIO) object code that enables a DTIO enabled processor to optimize execution of DTIO instructions. A code sequence configured to facilitate DTIO in a DTIO enabled processor is identified by a computer. The code sequence includes an internal representation (IR) of a first instruction and an IR of a second instruction. The second instruction is dependent on the first instruction. A schedule associated with at least one of the IR of the first instruction and the IR of the second instruction is modified. The modifying includes generating a modified schedule that is configured to place the first instruction next to the second instruction. An object file is generated based on the modified schedule. The object file includes the first instruction placed next to the second instruction. The object file is emitted.

Compiling code for an enhanced application binary interface (ABI) with decode time instruction optimization

Embodiments of the invention provide a means for verifying that a person using a bank card at a point-of-sale merchant location is in fact a person authorized to use the bank card. In one embodiment of the invention, verification may involve communicating with the mobile deviceassociated with the person authorized to use the bank card. The person authorized to use the bank card may be required to send verification data to the bank card verification system via the mobile device to confirm a purchase. The bank card verification system may not authorize the purchase if the proper verification data is not received from the mobile device. In another embodiment, the bank card verification system may be configured to determine a proximity of the mobile device to the merchant point-of-sale location to verify the purchase.

Real-time security verification for banking cards

A code sequence made up multiple instructions and specifying an offset from a base address is identified in an object file. The offset from the base address corresponds to an offset location in a memory configured for storing an address of a variable or data. The identified code sequence is configured to perform a memory reference function or a memory address computation function. It is determined that the offset location is within a specified distance of the base address and that a replacement of the identified code sequence with a replacement code sequence will not alter program semantics. The identified code sequence in the object file is replaced with the replacement code sequence that includes a no-operation (NOP) instruction or having fewer instructions than the identified code sequence. Linked executable code is generated based on the object file and the linked executable code is emitted.

Compiling code for an enhanced application binary interface (ABI) including identifying, by a computer, a code sequence configured to perform a variable address reference table function including an access to a variable at an offset outside of a location in a variable address reference table. The code sequence includes an internal representation (IR) of a first instruction and an IR of a second instruction. The second instruction is dependent on the first instruction. A scheduler cost function associated with at least one of the IR of the first instruction and the IR of the second instruction is modified. The modifying includes generating a modified scheduler cost function that is configured to place the first instruction next to the second instruction. An object file is generated responsive to the modified scheduler cost function. The object file includes the first instruction placed next to the second instruction. The object file is emitted.

Linking code for an enhanced application binary interface (ABI) with decode time instruction optimization

OOP environments comprise composite data structures and internal mechanisms for manipulating those structures. The structures are used to allow a user to realize the power of OOP. Hence, the layout of these structures, the way in which the structures inter-relate, and the manner in which they are built and used are all critical to the utility of a particular OOP environment. It is no surprise, then, that manufacturers and suppliers of OOP environments are constantly striving to design composite data structures and internal mechanisms which maximize user productivity. The internal mechanisms and structures that make up the present invention are collectively referred to as the New Object Model (NOM). The composite data structures and organization of the NOM OOP environment provide significant benefits that are not provided by the environments of the prior art. These benefits include: a more efficient method resolution scheme and the ability to add method programs and object instance data to a class definition without the need to recompile the majority of the code base.

Efficient method router that supports multiple simultaneous object versions

A multi-tasking computer operating system allocates a respective virtual address space to each task. A portion of virtual address space is reserved as a shared address space (SAS) region, the SAS region occupying the same range of virtual addresses in the virtual address space of each task. Certain classes of data intended for sharing among multiple tasks are assigned unique and persistent addresses in the range of the shared address space region. Preferably, certain facilities are added to a conventional base operating system to support the SAS region and associated function. These include a join facility for initiating a task to the SAS region, an attach facility for attaching blocks of memory within the SAS region, and a paging facility for retrieving a page within the SAS region from storage. In this manner, it is possible for a multi-tasking multiple virtual address space computer system to assume the advantages of a single level store computer system when performing certain tasks.

Computer system having shared address space among multiple virtual address spaces

This present invention incorporates the benefits of the function shipping, page shipping and class shipping remote object access models into a single, industry standard programming model. The fundamental mechanism of the present invention is an underlying shipper mechanism, which dynamically selects and updates the remote object access method being employed for any given access based on the most desirable method available at the time of the object access. The shipper mechanism dynamically decides which underlying access mechanism to use based on (1) object access policy rules, and (2) system operational loads and network traffic heuristics. The shipper is further capable of transparently switching from one access model to another while an object access is on-going.

Object access mechanism that dynamically switches between multiple distributed access models

The present invention utilizes a hardware Window Storage Protection Controller (WSPC) and an Object Encapsulation Enforcement Manager (OEEM) to limit access to object data to only those methods which are encapsulated by the object All of the objects of the computer system which require protection are stored in protected storage by a base storage protection mechanism so that only the mechanisms of the present invention can deny or permit access to the data encapsulated by the objects.

Object encapsulation protection apparatus

A preferred embodiment of the present invention provides an intelligent reference object (IRO), which is used to encapsulate address translation between shared address space (SAS) addresses and native system addresses. The IRO works with a shared persistent virtual storage system that provides address translation between SAS addresses and the underlying system. By encapsulating these addresses translations in an IRO, the preferred embodiment provides the ability to create and share persistent objects using single level store semantics. When a client accesses the data in a persistent object, the IRO corresponding to the persistent object provides any address translation and indirection needed to perform the access.

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Rochester, MN, United States of America

Steven Jay Munroe