Nvidia Corporation

3dlabs Inc., Ltd.

Intergraph Corporation

Steven James Heinrich

Shirish C Gadre

Michael Alan Fetterman

Omkar Paranjape

Rajeshwaran Selvanesan

Stewart Glenn Carlton

Anjana Rajendran

Charles McCarver

Jack H Choquette

Dale L Kirkland

Alexander Lev Minkin

James Leroy Deming

Clifford A Whitmore

Poornachandra Rao

Matt E Buckelew

Ramesh Jandhyala

John H Edmondson

Xiaogang Qiu

Eric Brian Lum

Eric Lyell Hill

Mark Alan Gebhart

Henry Packard Moreton

Brett Coon

John R Nickolls

Yury Y Uralsky

Patrick Richard Brown

Olivier Giroux

Manan Patel

Stewart G Carlton

Douglas J Hahn

Mark Allen Mosley

Timothy S Johnson

Emmett Michael Kilgariff

Jeffrey A Bolz

Ronny Krashinsky

Stefano A Pescador

Andrew Robert Kerr

Jonathan J Dunaisky

Alan Kaatz

Michael S Farmer

Kevin Mitchell

Michael Siu

Ming Yiu Siu

Rui Manuel Bastos

Michael C Shebanow

Joel James McCormack

Tyson J Bergland

Liang Yin

Yan Yan Tang

David Charles Patrick

Tomas G Akenine-Moller

Nirmal Raj Saxena

Brian Matthew Fahs

Wishwesh Anil Gandhi

Naveen Cherukuri

Bengt-Olaf Schneider

Bryon S Nordquist

Eric T Anderson

Peter C Mills

Robert Steven Glanville

Robert J Stoll

James Robertson

Walter Robert Steiner

Gentaro Hirota

Nicholas Wang

Martin Stich

Praveen Krishnamurthy

Praveen Joginipally

Ram Rangan

Vaishali Kulkarni

Adam Hendrickson

Sandeep Navada

William Newhall

Dong Han Ryu

Raghavan Madhavan

Saurabh Hukerikar

Paul Racunas

William R Lazenby, Jr

Mitchell Hayenga

Poorna Rao

Abhijeet Ghadge

Yiyang Feng

Jeff Bolz

Mathias Heyer

Aravind Kalaiah

Daniel Salinas

Tommy Thorn

Brett W Coon

Various embodiments include techniques for managing cache memory in a computing system. The computing system includes a sectored cache memory that provides a mechanism for software applications to directly invalidate data items stored in the cache memory on a sector-by-sector basis, where a sector is smaller than a cache line. When all sectors in a cache line have been invalidated, the cache line is implicitly invalidated, freeing the cache line to be reallocated for other purposes. In cases where the data items to be invalidated can be aligned to sector boundaries, the disclosed techniques effectively use status indicators in the cache tag memory to track which sectors, and corresponding data items, have been invalidated by the software application. Thus, the disclosed techniques thereby enable a low-overhead solution for invalidating individual data items that are smaller than a cache line without additional tracking data structures or consuming additional memory transfer bandwidth.

Cache memory with per-sector cache residency controls

Various embodiments include a system for managing cache memory in a computing system. The system includes a sectored cache memory that provides a mechanism for sharing sectors in a cache line among multiple cache line allocations. Traditionally, different cache line allocations are assigned to different cache lines in the cache memory. Further, cache line allocations may not use all of the sectors of the cache line, leading to low utilization of the cache memory. With the present techniques, multiple cache lines share the same cache line, leading to improved cache memory utilization relative to prior techniques. Further, sectors of cache allocations can be assigned to reduce data bank conflicts when accessing cache memory. Reducing such data bank conflicts can result in improved memory access performance, even when cache lines are shared with multiple allocations.

Hybrid allocation of data lines in a streaming cache memory

A technique for block data transfer is disclosed that reduces data transfer and memory access overheads and significantly reduces multiprocessor activity and energy consumption. Threads executing on a multiprocessor needing data stored in global memory can request and store the needed data in on-chip shared memory, which can be accessed by the threads multiple times. The data can be loaded from global memory and stored in shared memory using an instruction which directs the data into the shared memory without storing the data in registers and/or cache memory of the multiprocessor during the data transfer.

Techniques for efficiently transferring data to a processor

Techniques are disclosed herein for interleaving textures. In the disclosed techniques, multiple textures that would otherwise be accessed separately are interleaved into a single, interleaved texture that can be used to access the multiple textures together. The interleaved texture can include alternating blocks from the multiple textures. The interleaved texture can be generated when the multiple textures are being loaded into memory. Further, the interleaved texture can be accessed using multiple texture headers that are associated with different textures in the interleaved texture. Each of texture headers includes a stride indicating the distance between two blocks from a same texture in the interleaved texture.

Techniques for interleaving textures

In a streaming cache, multiple, dynamically sized tracking queues are employed. Request tracking information is distributed among the plural tracking queues to selectively enable out-of-order memory request returns. A dynamically controlled policy assigns pending requests to tracking queues, providing for example in-order memory returns in some contexts and/or for some traffic and out of order memory returns in other contexts and/or for other traffic.

Out of order memory request tracking structure and technique

Various embodiments include a parallel processing computer system that detects memory errors as a memory client loads data from memory and disables the memory client from storing data to memory, thereby reducing the likelihood that the memory error propagates to other memory clients. The memory client initiates a stall sequence, while other memory clients continue to execute instructions and the memory continues to service memory load and store operations. When a memory error is detected, a specific bit pattern is stored in conjunction with the data associated with the memory error. When the data is copied from one memory to another memory, the specific bit pattern is also copied, in order to identify the data as having a memory error.

Error containment for enabling local checkpoint and recovery

A texture processing pipeline in a graphics processing unit generates the surface appearance for objects in a computer-generated scene. This texture processing pipeline determines, at multiple stages within the texture processing pipeline, whether texture operations and texture loads may be processed at an accelerated rate. At each stage that includes a decision point, the texture processing pipeline assumes that the current texture operation or texture load can be accelerated unless specific, known information indicates that the texture operation or texture load cannot be accelerated. As a result, the texture processing pipeline increases the number of texture operations and texture loads that are accelerated relative to the number of texture operations and texture loads that are not accelerated.

Techniques for performing accelerated point sampling in a texture processing pipeline

Some systems compress data utilized by a user mode software without the user mode software being aware of any compression taking place. To maintain that illusion, such systems prevent user mode software from being aware of and/or accessing the underlying compressed states of the data. While such an approach protects proprietary compression techniques used in such systems from being deciphered, such restrictions limit the ability of user mode software to use the underlying compressed forms of the data in new ways. Disclosed herein are various techniques for allowing user-mode software to access the underlying compressed states of data either directly or indirectly. Such techniques can be used, for example, to allow various user-mode software on a single system or on multiple systems to exchange data in the underlying compression format of the system(s) even when the user mode software is unable to decipher the compression format.

Techniques for accessing and utilizing compressed data and its state information

A unified cache subsystem includes a data memory configured as both a shared memory and a local cache memory. The unified cache subsystem processes different types of memory transactions using different data pathways. To process memory transactions that target shared memory, the unified cache subsystem includes a direct pathway to the data memory. To process memory transactions that do not target shared memory, the unified cache subsystem includes a tag processing pipeline configured to identify cache hits and cache misses. When the tag processing pipeline identifies a cache hit for a given memory transaction, the transaction is rerouted to the direct pathway to data memory. When the tag processing pipeline identifies a cache miss for a given memory transaction, the transaction is pushed into a first-in first-out (FIFO) until miss data is returned from external memory. The tag processing pipeline is also configured to process texture-oriented memory transactions.

Unified cache for diverse memory traffic

Methods and apparatuses are disclosed for reporting texture footprint information. A texture footprint identifies the portion of a texture that will be utilized in rendering a pixel in a scene. The disclosed methods and apparatuses advantageously improve system efficiency in decoupled shading systems by first identifying which texels in a given texture map are needed for subsequently rendering a scene. Therefore, the number of texels that are generated and stored may be reduced to include the identified texels. Texels that are not identified need not be rendered and/or stored.

Method and apparatus for obtaining sampled positions of texturing operations

Growing community of inventors

Madison, AL, United States of America

Steven James Heinrich