Intel Corporation

Marvell International Limited

Steven J Tu

David E Miner

Sujat Jamil

Hang T Nguyen

R Frank O'Bleness

Samantha J Edirisooriya

Scott W Murray

Satyajit Mohapatra

Dmitrii A Loukianov

Gregory W Tse

Alexander J Honcharik

Joseph G Warner

Mark Norman Fullerton

Tse-Yu Yeh

Jorge E Caviedes

Gregory Scott Mathews

Jason Sandri

Quinn W Merrell

Yan Xu

Orlando Davila

Alexander Honcharik

Non-processor agents, such as bus agents, may directly access processor caches. A coherency protocol ensures that cache coherency is maintained.

Implementing direct access caches in coherent multiprocessors

According to some embodiments, a video block memory read request may be received from a processing unit. For example, a codec may request to access a macroblock of pixel information from a memory unit. The video block memory read request may then be translated into a plurality of memory access requests.

Video block memory read request translation and tagging

According to some embodiments, encoded information associated with an image is received at a decoder. The encoded information may be decoded at the decoder to generate full-sized first image pixels representing a full-sized version of the image. Moreover, the full-sized pixels may be scaled at the decoder to generate scaled image pixels representing a scaled version of the image.

Digital image decoder with integrated concurrent image prescaler

A semiconductor chip is described having a plurality of processing cores. The semiconductor chip also includes a plurality of test controllers. Each test controller is associated with a different one of the processing cores. The semiconductor chip also includes a test port having a first serial input and a first serial output. The first serial input is to receive serial test input data provided to the semiconductor chip. The first serial output is to provide serial output data provided by the semiconductor chip. The semiconductor chip further includes switch circuitry coupled to the test port and the plurality of test controllers. The switch circuitry is to route the serial test input data to one of the plurality of test controllers and to route the serial output data from one of the plurality of test controllers to the first serial output. The semiconductor chip further includes a configuration register coupled to the switch circuitry to establish the switch circuitry's routing configuration.

Test access port

A method and apparatus for power optimized replay. In one embodiment, the method includes the issuance of an instruction selected from a queue. Once issued, the instruction may be enqueued within a recirculation queue if completion of the instruction is blocked by a detected blocking condition. Once enqueued, instructions contained within the recirculation queue may be reissued once a blocking condition of an instruction within the recirculation queue is satisfied. Accordingly, a power optimized replay scheme as described herein optimizes power while retaining the advantages provided by selectively replaying of blocked instructions to improve power efficiency.

Power optimized replay of blocked operations in a pipilined architecture

Pipelining techniques to deinterlace video information are described. An apparatus may comprise deinterlacing logic to convert interlaced video data into deinterlaced video data using multiple processing pipelines. Each pipeline may process the interlaced video data in macroblocks. Each macroblock may comprise a set of working pixels from a current macroblock and supplemental pixels from a previous macroblock. Other embodiments are described and claimed.

Pipelining techniques for deinterlacing video information

According to some embodiments, a first bus may be monitored, the first bus being to exchange data between a first processing system and a second processing system. A second bus may also be monitored, the second bus being to exchange data between the second processing system and a third processing system. Responsive to the monitoring of at least one of the first or second buses, execution of applications, executing on at least two of the processing units, may be interrupted.

Transactional flow management interrupt debug architecture

A method including, in some embodiments, comparing a preceding field and a succeeding field of a video signal for motion at a locus of a current pixel in a current field to be interpolated, in an instance of no motion determining which of a current pixel location in the preceding field and the succeeding field is closer to an estimate of a neighbor pixel and using the result of the determination to decide which of the preceding and succeeding fields to use to interpolate the current pixel based on symmetric spatial neighbors of the current pixel, and in an instance of motion interpolating the current pixel based on symmetric spatial neighbors of the current pixel at a line above and a line below the current pixel in the current frame.

Spatio-temporal adaptive video de-interlacing for parallel processing

A bus control system includes N bus agents each having a corresponding bus request delay and M bus agents each having a corresponding bus request delay. A controller determines the bus request delays of the N bus agents and the M bus agents and grants concurrent ownership of a bus to each of the N bus agents and non-concurrent ownership of the bus to each of the M bus agents based on the determination. M and N are integers greater than 1.

Apparatus and method for arbitrating heterogeneous agents in on-chip busses

A method and apparatus for optimizing line writes in cache coherent systems. A new cache line may be allocated without loading data to fill the new cache line when a store buffer coalesces enough stores to fill the cache line. Data may be loaded to fill the line if an insufficient number of stores are coalesced to fill the entire cache line. The cache line may be allocated by initiating a read and invalidate request and asserting a back-off signal to cancel the read if there is an indication that the coalesced stores will fill the cache line.

Method and apparatus for optimizing line writes in cache coherent systems

Apparatus and method for power optimized replay via selective recirculation of instructions

A system, method, and apparatus for a cache memory to support a low power mode of operation.

Cache memory to support a processor's power mode of operation

Some embodiments of the invention include an address interconnect and a data interconnect to transfer data among a number of devices. The data interconnect is configured to transfer data among the devices via multiple transfer paths. A transfer of data on one transfer path is independent from a transfer of data on another transfer path. In some cases, data is concurrently transferred among more than two of the devices on at least one of the address interconnect and the data interconnect. Other embodiments are described and claimed.

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Phoenix, AZ, United States of America

Steven J Tu