Texas Instruments Corporation

Steven J Tinsley

Mark William Morgan

Julie Hwang

Fernando D Carvajal

Hector Torres

James Dietz

Julie A Hwang

An apparatus for handling high speed data communication signals in at least one input channel. Each communication signal is encoded in signal excursions in at least one predetermined format. The apparatus includes: (a) at least one input locus coupled with each input channel for receiving the signals; (b) at least one output locus for presenting selected communication signals in a desired format in at least one output channel; and (c) a plurality of treating circuits for treating the signal excursions in a plurality of formats that include the predetermined format and the desired format. Each treating circuit is coupled with at least one respective input locus and at least one respective output locus. The apparatus presents sufficiently low capacitance between input loci and output loci to impart substantially zero time delay to the communication signals.

Apparatus for handling high speed data communication signals and method for manufacture thereof

The present invention provides a method, system and apparatus for providing failsafe detection for a differential receiver. A bus activity signal () is activated when receiving a differential data signal of sufficient amplitude to transition through a predetermined threshold. A failsafe signal () indicates a low differential voltage condition. A countdown time period commences () upon activation of either signal, and a failsafe condition is determined () to exist if the failsafe signal is active () when the countdown time period expires ().

Active failsafe detection for differential receiver circuits

A system and method is described for a driver circuit used for high speed data transmission in LVDS and CML transceiver device applications. The transceivers are intended to receive a low voltage differential input signal and interchangeably drive a standard LVDS load with a TIA/EIA-644 compliant LVDS signal, and a standard CML load with a standard CML compatible signal. The driver circuit operates at speeds up to 1.36 Gbps, making it compatible with the OC-24 signaling rate for optical transmission. To accomplish this, the driver uses a mixed combination of voltage and current mode drive sections in the output circuit when coupled to LVDS loads, and when the driver is coupled to CML loads, operates purely in a current mode using only the current mode drive section. MOS transistors and a current source are used in the current mode switch portion to switch the drive with a constant current at the high speeds, and NPN transistors in the voltage mode output portion provide variable impedance for the output circuit. A common mode compensation circuit using a feedback voltage from the load generates a compensation signal for variable impedance control of the NPN transistors to yield a regulated voltage for the common mode dc voltage.

Interchangeable CML/LVDS data transmission circuit

A driver ( ) which meets wide common mode voltage requirements is provided. Output passgates ( ) protect sensitive line driver circuitry ( ) from extreme bus voltages; enabling/disabling circuits ( ) detect fault conditions to ensure the line driver is disabled when needed, and pull-ups ( ) assist in line driver start up by preventing negative voltage conditions on the bus driven by the line driver.

Extended common mode differential driver

A circuit that provides a stable predrive to a BiCMOS LVDS output which compensates for supply voltage variations while maintaining a suitably fast signal path. The supply voltage compensation circuit provides an offset to the predrive level shift such that when the supply voltage V rises, the predrive output voltage is lowered in response.

Supply voltage compensation circuit for high speed LVDS predrive

The present invention provides improved slew rate control over a varied operating temperature range. A switching device (P , N ) receives from a predrive circuit ( ) a control signal that limits a slew rate of the switching device's output and also varies proportionally to the operating temperature. In this manner, the effect of temperature on the slew rate can be reduced.

Temperature compensated slew rate control circuit

The output slew rate of a differential transmission line driver ( ) can be limited by suitably controlling signal slew rates ( ) at the control inputs (neg, pos) of the drive switches (M -M ) that control current flow through the load impedance (Rload) of the driver.

Output slew rate control for a differential transmission line driver

A fast voltage differential signaling (LVDS) transceiver ( ) having high repeater speeds up to 1.36 GBps, and also meeting the TIA/EIA-644 standard short-to-ground requirements. A mixed voltage-current mode differential driver has a respective control signal (A ) driving each of the drive transistors (Q ). The control signal (A ) is controlled by a transistor (M ) being a function of current through the respective drive transistor (Q ). A current mirror (Q , Q , Q ) is used to mirror current conducting through a transistor (Q ) in parallel with the drive transistor (Q ), which mirror current is compared against a current reference (Iref).

Voltage/current mode TIA/EIA-644 compliant fast LVDS driver with output current limit

A low-current oscillator with input buffer hysteresis for increased noise immunity during oscillator start-up. Resistors are switched in and out of the comparator input elements creating offsets in one leg of the comparator at a time.

Low-current oscillator with hysteresis input buffer

A CMOS oscillator includes two differential input transistors (150) and (152) which have the sources thereof coupled through a resonator element (196). Active loads (166) and (178) provide a squaring up of the output which then drives an output transistor (202). The gates of the differential input transistors (150) and (152) are biased to predetermined voltage levels with bias circuits, with the positive input of the comparator configuration coupled through a feedback capacitor (208) to the output (204). This provides sufficient instability to initiate oscillation with a gain of the device controlled by resonator circuit (196) to be optoimum at the resonant frequency of the resonator circuit.

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Garland, TX, United States of America

Steven J Tinsley