International Business Machines Corporation

Analog Devices International Unlimited Company

Linear Technology Corporation

Linear Technology Holding LLC

Steven J Tanghe

Brian Kirk Jadus

Anthony Richard Bonaccio

Charles Joseph Masenas

Kenneth G Richardson

Gregg R Castellucci

Sharon Lynne Von Bruns

Arnold E Baizley

Scott M Parker

Michael Collins

Deepak Gunasekaran

Wilbur David Pricer

Patrick Martin McGuinness

Michel S Michail

Ciaran J Brennan

Chad Edward Mitchell

Kevin R Wrenner

Michael Amato

Art Zirger

Gregg R Castellucei

Richard T Kaul

Patrick M Mcguinness

Brian K Jadus

An apparatus and methods to operate the same to provide fast fault-detection on power semiconductor devices such as power transistors are disclosed. In some embodiment, a desaturation based fault-detection circuit for a power transistor is provided. The fault-detection circuit has an adaptable blanking time and a disconnect switch in the blanking mechanism that allow for quick enabling of fault-detection mechanisms to achieve fast fault detection times on power semiconductor devices.

Apparatus and method to achieve fast-fault detection on power semiconductor devices

Isolators having a back-to-back configuration for providing electrical isolation between two circuits are described, in which multiple isolators formed on a single monolithic substrate are connect in series to achieve a higher amount of electrical isolation for a single substrate than for one of the isolators alone. A pair of isolators in the back-to-back configuration have top and bottom isolator components where the top isolator components are connected together and electrically isolated from the underlying substrate, resulting in floating top isolator components. The back-to-back isolator may provide one or more communication channels for transfer of information and/or power between different circuits.

Monolithic back-to-back isolation elements with floating top plate

A circuit to control a switching characteristic of a switching device. The circuit includes a driver circuit comprising an output port, where the driver circuit is configured to generate, at the output port, a control signal to actuate the switching device within a first time period. The control signal comprising at least one electrical pulse, where a pulse width of the at least one electrical pulse being shorter than the first time period. The circuit also includes a coupling circuit that is configured to use the control signal to actuate the switching device to establish a target switching characteristic of the switching device according to a modulation of the at least one electrical pulse. The control circuit is also configured to provide a greater impedance to the control signal than an impedance of the output terminal of the driver circuit.

Gate driver with pulsed gate slew control

An electronic circuit comprises a power switch and a fault detection circuit. The power switch circuit includes a power switch transistor. The fault detection circuit includes a comparator circuit configured to monitor a voltage across the power switch transistor and compare the voltage to a varying threshold voltage that decreases with time, and produce an indication of a circuit fault when the voltage of the power switch transistor is greater than the time varying threshold voltage.

Overcurrent protection detector with dynamic threshold for power conversion switch

An electronic circuit comprises a power switch circuit and a fault detection circuit. The power switch circuit includes a transistor. The fault detection circuit includes a first comparator circuit configured to compare a monitored voltage of the transistor to a detection threshold voltage and produce an indication of a circuit fault according to the comparing, and a delay circuit configured to delay the comparing by the first comparator circuit according to slew rate of the monitored voltage.

Adaptive blanking of over current fault detection circuits in power conversion gate drivers

The subject technology provides for an architecture that isolates two interfaces of a circuit with an isolating communication element while also protecting against overstress transients such as electro-static discharge (ESD) and other electrical overstress (EOS) transients across the isolating communication element that can be significantly larger than the ESD rating of the isolating communication element, and/or that may be repeated in succession. The subject technology provides isolation using a two die implementation with an isolation interface including an isolation tub in each die, or a single die containing both isolation tubs in the die. The two dice include respective substrates that are connected together and float with respect to any signal or ground. The isolation enables a large offset voltage on the order of hundreds of volts to exist between the sides. Being relatively large, each isolation tub can handle a significant amount of energy.

Isolation architecture

A transceiver capable of common mode operating range and output voltage tolerance set by an isolation boundary and not limited by the device type used in the circuitry. The subject technology is a powered isolated transceiver, where the isolated generated supply and ground nodes are concealed and thus do not participate in tests that stress electrostatic discharge (ESD)/electrical overstress (EOS) or voltage tolerance. The architecture of the subject technology has the advantage of extremely high common mode performance and robust performance using low voltage devices and simplified architecture, which in turn provides less capacitive loading, faster operation, less expensive die development, electromagnetic interference (EMI) advantages, and simple active termination. The subject technology includes an isolation architecture that can be used in environments where isolation is used but is also advantageous in systems without the need for isolation.

Transceiver utilizing isolated signaling and concealed isolated power to attain high common mode working voltage and tolerance

Multiple termination impedance values are provided in a switchable termination circuit so as to accommodate multiple transmission line characteristics. In one example, a termination matching circuit includes first and second nodes, a series interconnection of a first switch and a first impedance coupled between the first and second nodes, and another series interconnection of a second switch and a second impedance coupled between the first and second nodes. First and second control circuits respectively control the first and second switches such that a selectable impedance is provided between the first and second nodes through selective activation of the first and second switch devices by the first and second control circuits. In another example, additional nodes and resistors are provided to provide further termination impedance values.

Switchable termination with multiple impedance selections

This disclosure describes a circuit implementation providing the functions necessary to implement an isolated IC bidirectional port. The technique implements a current source as a pull up device on at least one side of the isolation system. The circuit manages and communicates bidirectional data across an isolation barrier. A method of communicating bidirectional signals and an IC acknowledge (ACK) or clock stretching through an isolation channel is disclosed.

[object Object]

A method and apparatus for testing ADC circuitry. The method and apparatus detects infrequently occurring errors by providing a series of waveforms to the ADC that have different amplitude, frequency, or voltage offset from one another. The outputs of the ADC for the waveforms are then analyzed for timing related errors.

Method and apparatus for testing analog to digital converters

A structure and method for a field effect transistor capable of handling high currents, comprises interleaved source and drain diffusion regions with drain diffusion contacts to a first metal level over the drain diffusions only; while a second metal level covers the full width of the device and takes current out of the source in a primarily vertical direction.

Asymmetrical MOSFET layout for high currents and high speed operation

A flash analog to digital converter includes a reference ladder, consisting primarily of resistors, a plurality of comparators, each coupled to a different reference voltage on the reference ladder (the comparators compare a received voltage with a reference voltage level developed across corresponding resistor or group of resistors), and a variable power source coupled to the reference ladder for varying the reference levels generated from the ladder. The structure includes a fixed (or variable) gain driver supplying the received signal voltage to the bank of comparators. The variable power source can be an adjustable current source or an adjustable voltage source. The comparators can be single-ended comparators or differential comparators.

Structure for adjusting gain in a flash analog to digital converter

A method and structure for calibrating an analog to digital converter comprises an input signal; a driver receiving the input signal, wherein the driver outputs a driver output signal; a flash circuit receiving the driver output signal, wherein the flash circuit outputs a comparison result equaling 2 &minus;1 digital outputs; an encoding logic unit encoding the comparison result into n digital bits as an output signal; a calibration engine outputting a calibration input adjust signal, a reference adjust signal, a driver gain adjust signal, a driver offset adjust signal; and a calibration input circuit receiving the calibration input adjust signal, wherein the driver receives the driver gain adjust signal and the driver offset adjust signal, wherein the flash circuit receives the reference adjust signal, wherein the calibration engine receives n digital bits, and controls an operation of the driver or flash circuit based on the output signal.

Method and circuit for dynamic calibration of flash analog to digital converters

A method and structure for an integrated circuit including a differential amplifier having at least two inputs and at least two outputs; a pair of first resistors, each of which is coupled to one of the inputs; a pair of first source followers, each of which is coupled to one of the first resistors; a pair of second source followers, each of which is coupled to one of the out puts; a pair of second resistors, each of which is coupled to one of the second source followers and to one of said inputs; and a gain device connected between the first resistors and the first source followers.

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Essex Junction, VT, United States of America

Steven J Tanghe