Hewlett-packard Company

Other

Steven J Kommrusch

Bradly J Foster

Howard D Stroyan

Daniel G Schmidt

S Paul Tucker

Milan Singh Minsky

Henry Bowdoin Minsky

Randy T Crane

Max Carlson

Cyrus Shaoul

David J Hodge

A method for training a learning system to identify components of time-based data streams includes processing, by a machine vision component in communication with a learning system, a video file to detect at least one object in the video file. The method includes generating by the machine vision component an output including data relating to the at least one object and the video file. The method includes analyzing, by a learning system, the output. The method includes identifying, by the learning system, an unidentified object in the processed video file.

Methods and systems for training and execution of improved learning systems for identification of components in time-based data streams

A segmented photosensor array for an image scanner has segments with imperfect alignment. During scanner manufacturing, photosensor segment alignment data, such as segment position offset and segment angle, is measured. The offset and angle are stored in non-volatile memory within the scanner. A position correction system uses the stored alignment data to correct position and angle values before being processed by a rectification system. Most pixels require simple geometry calculations. However, a more complex state machine is needed to handle the transition from one photosensor segment to the next. Correcting for segment position offset and angle errors enables a cost reduction for the sensor array and, in particular, reduces costs associated with scrap.

Digital image scanner with compensation for misalignment of photosensor array segments

A computer graphics system includes an apparatus for fog blending colors to be displayed on a graphics display of the computer graphics system. The computer graphics system includes a rendering parameter calculation unit responsive to data of a primitive, that determines a cooked exponent value and a color value for at least one pixel of the primitive. In addition, the system includes a fog unit responsive to the cooked exponent value for each pixel of the primitive, that determines a fog blending factor for each pixel of the primitive, wherein the fog blending factor is one of an exponential fog blending factor and an exponential-squared fog blending factor. Further, the system includes a fog blending unit responsive to the color value and the fog blending factor for each pixel of the primitive and also to a fog color value, that blends the fog color value with the color value for each pixel of the primitive according to the fog blending factor for the respective pixel, and that provides a fogged color value for each pixel of the primitive. In addition, the computer graphics system may include a first interpolator, responsive to the color value and the cooked exponent value for at least one pixel of the primitive, that determines the color value and the cooked exponent value along an edge of the primitive so as to provide the cooked exponent value and the color value for each pixel of the edge of the primitive. Further, the computer graphics system may also include a second interpolator, responsive to the cooked exponent value and the color value for each pixel of the edge of the primitive, that determines the cooked exponent value and the color value along a span of the primitive so as to provide the cooked exponent value and the color value for each pixel of the span of the primitive. In this way, the system provides fast and accurate exponential and exponential-squared fog blending of the color values of the primitive without a lot of hardware.

Computer graphics system having per pixel fog blending

A voltage shift feedback system offsets the signal amplitude of an incoming analog video signal so that a more accurate analog-to-digital conversion of the analog video signal can be achieved in an analog-to-digital convertor. The voltage shift feedback system comprises an input capacitor for isolating the system from the analog video signal and a feedback loop. The feedback loop comprises a separator mechanism in the preferred embodiment for determining when the analog video signal exhibits a particular amplitude, such as a blank level or a synchronization level, and for generating a separator output indicative thereof. An offset control logic monitors the digital pixel data output from the ADC and the separator output. A variable current mechanism is connected to the offset control logic and the ADC input connection for supplying a continuous current i.sub.c to the ADC input. When the analog video signal exhibits the particular amplitude, the offset control logic compares the digital pixel data from the ADC to a predetermined range, preferably a desired synchronization or blank amplitude range, and adjusts the current so that the digital pixel data converges toward the predetermined range.

Constant current voltage restoration

A dot clock generation system has a voltage-controlled oscillator (VCO) for generating a dot clock signal for an analog-to-digital convertor (ADC). A dot clock synchronization (sync) generator counts cycles of the dot clock signal and generates a dot clock sync signal. An analog video signal is passed through a first differential buffer to create an analog video sync signal. The analog video sync signal is passed through a first flip-flop storage element to a phase detector. The dot clock sync signal is passed through a second storage element and then through a second differential buffer to the phase detector. The second storage buffer insures that the edge of the dot clock sync signal which is used by the phase detector is tightly tied with the sampling edge of the dot clock signal which is used by the ADC to sample the analog data within the analog video signal. Moreover, the first and second buffers and storage elements introduce similar propagation time delays into the analog video sync signal and the dot clock sync signal. Accordingly, the phase detector accurately compares the phases of these sync signals and generates a highly accurate voltage control signal for the voltage-controlled oscillator, thereby resulting in a high precision dot clock signal.

Dot clock generation with minimal clock skew

A computer graphics system and method for capping a polyhedron made up of a plurality of polygons after the polyhedron has been sectioned by a designer to thereby provide a realistic display of the polyhedron. The computer graphics system first comprises at least one processor and at least one memory unit configured with the computer graphics system to process data. The computer graphics system further comprises an input device configured with the computer graphics system to allow the designer to specify the at least one sectioning plane. The computer graphics system further comprises a polyhedron capping module configured in the computer graphics system to instruct the at least one processor how to section and cap the polyhedron against the sectioning plane. The computer graphics system further comprises a display device configured with the computer graphics system to display the capped polyhedron.

Computer graphics system and method for capping volume enclosing

A synchronization (sync) separation system and method quickly and accurately generate a sync signal from an analog video signal by using feedback control. The system comprises a voltage generator for generating first and second reference voltages V.sub.REF1, V.sub.REF2. A first comparator compares the analog video signal to the first reference voltage V.sub.REF1 and generates a shift control signal, A voltage shift mechanism receives the shift control signal and adjusts the analog video signal so that the sync level of the analog video signal converges toward the first reference voltage V.sub.REF1. A second comparator compares the analog video signal with the second reference voltage V.sub.REF2 and generates the sync signal indicative of when the analog video signal exhibits the sync level. Preferably, the voltage shift mechanism introduces a continuous current i.sub.c into the analog video signal. Moreover, the second comparator is an ECL differential line receiver in the preferred embodiment for providing a sync signal which is compatible with ECL.

High speed sync separation system and method

A frame rate conversion system synchronizes data transfers to and from a VRAM frame buffer which are concurrent, continuous, and asynchronous. The system comprises a frame buffer having a split memory for communicating data to a split output shift register. A frame buffer control supervises writing operations to the split memory at a first frame rate. A display control supervises reading operations from the shift register at a second frame rate which is slower than the first frame rate. The frame buffer control and the display control communicate control signals through double synchronizers. The display control has a counter for counting frames of data which have been read from the VRAM frame buffer. The display control prevents the writing of a frame into the split memory after a particular number of frames has been counted so as to prevent the frame buffer control from writing over and destroying existing data which has not yet been read from the split memory by the display control. Moreover, the display control synchronizes the writing and reading operations by the frame buffer control and the display control, respectively, each time that a frame has been skipped. Furthermore, the frame buffer control causes the VRAM frame buffer to transfer data from the split memory to the shift register when the horizontal blank is deasserted within the incoming analog video signal.

Frame rate conversion with asynchronous pixel clocks

A computer graphics system configured to allow a user to move at least one sectioning plane about at least one polyhedron having a plurality of polygons and to display, if necessary, an interference area between the plurality of polygons is disclosed. The computer graphics system first comprises at least one processor and at least one memory unit configured with the computer graphics system to process data. The computer graphics system further comprises an input device configured with the computer graphics system to allow the user to specify the at least one sectioning plane. The computer graphics system further comprises an interference checking module configured with the computer graphics system to generate an interference cap polygon indicative of the interference area. The computer graphics system further comprises a display device configured with the computer graphics system to display the interference cap polygon.

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Ft. Collins, CO, United States of America

Steven J Kommrusch