Intel Corporation

Steven J Keating

Tahir Ghani

Chia-Hong Jan

Alan M Myers

Simon Yang

Julie A Tsai

Kevin A Whitehill

Brian S Doyle

Jack T Kavalieros

Mark L Doczy

Justin K Brask

Nick Lindert

Chris E Barns

Michael L McSwiney

John P Barnak

Anand S Murthy

Swaminathan Sivakumar

Satyarth Suri

Nadia M Rahhal-Orabi

Lana Jong

Lin Sha

Willy Rachmady

Mark T Bohr

Thomas A Letson

Donald W O'Neill

Robert S Chau

Boyan Boyanov

Christopher J Jezewski

Reza Arghavani

Joseph M Steigerwald

Timothy E Glassman

Douglas W Barlage

Chris Auth

Travis J Delashmutt

Michael Mcswiney

A method of patterning a metal () on a vertical sidewall () of an excavated feature () includes placing a material () in the excavated feature such that a portion () of the metal is exposed in the excavated feature above the material, etching the exposed portion of the metal away from the vertical sidewall using a first wet etch chemistry, and removing the material from the excavated feature by etching it away using a second wet etch chemistry. The described method may be used to produce a MIM capacitor () suitable for an eDRAM device.

Embedded memory device having MIM capacitor formed in excavated structure

Methods to form memory devices having a MIM capacitor with a recessed electrode are described. In one embodiment, a method of forming a MIM capacitor with a recessed electrode includes forming an excavated feature defined by a lower portion that forms a bottom and an upper portion that forms sidewalls of the excavated feature. The method includes depositing a lower electrode layer in the feature, depositing an electrically insulating layer on the lower electrode layer, and depositing an upper electrode layer on the electrically insulating layer to form the MIM capacitor. The method includes removing an upper portion of the MIM capacitor to expose an upper surface of the electrode layers and then selectively etching one of the electrode layers to recess one of the electrode layers. This recess isolates the electrodes from each other and reduces the likelihood of a current leakage path between the electrodes.

Methods to form memory devices having a capacitor with a recessed electrode

Method of patterning a metal on a vertical sidewall of an excavated feature, method of forming an embedded MIM capacitor using same, and embedded memory device produced thereby

Embodiments are an improved transistor structure and the method of fabricating the structure. In particular, a wet etch of an embodiment forms source and drain regions with an improved tip shape to improve the performance of the transistor by improving control of short channel effects, increasing the saturation current, improving control of the metallurgical gate length, increasing carrier mobility, and decreasing contact resistance at the interface between the source and drain and the silicide.

Transistor with improved tip profile and method of manufacture thereof

Methods and associated structures of forming a microelectronic device are described. Those methods may include utilizing a cleaning mixture comprising a solvent such as ethylene glycol monopropyl ether, an inorganic base, an organic base, a copper corrosion inhibitor and a surfactant to clean at least one of a polymer residue, a organic sacrificial fill material and etched or un-etched photo resist from a Damascene structure of a microelectronic structure comprising a porous oxide dielectric.

Chemistry for removal of photo resist, organic sacrificial fill material and etch polymer

At least a p-type and n-type semiconductor device deposited upon a semiconductor wafer containing metal or metal alloy gates. More particularly, a complementary metal-oxide-semiconductor (CMOS) device is formed on a semiconductor wafer having n-type and p-type metal gates.

Integrating n-type and p-type metal gate transistors

A method and device for improved salicide resistance in polysilicon gates under 0.20 &#x3bc;m. The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure with recessed thick inner spacers and thick outer spacers. Another embodiment provides a gate electrode structure with recessed thin inner spacers and recessed thick outer spacers. Another embodiment provides a gate electrode structure with thin inner spacers and partially recessed outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack within inner spacers and thin outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with recessed thin inner spacers and recessed thin outer spacers.

Device having recessed spacers for improved salicide resistance on polysilicon gates

Methods of forming an amorphous etch stop layer by implanting a substrate with an element that is electrically neutral within the substrate are described. The use of elements that are electrically neutral within the substrate prevents electrical interference by the elements if they diffuse to other areas within the substrate. The amorphous etch stop layer may be used as a hard mask in the fabrication of transistors or other devices such as a cantilever.

Amorphous etch stop for the anisotropic etching of substrates

integrating n-type and P-type metal gate transistors

Polysilicon formed over an underlying insulator may be highly selectively etched. This may permit the replacement of polysilicon gate electrode material, implementing a dual layer process or any of a variety of other applications.

Selective etching of polysilicon

A method and device for improved salicide resistance in polysilicon gates under 0.20 &mgr;m. The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure with recessed thick inner spacers and thick outer spacers. Another embodiment provides a gate electrode structure with recessed thin inner spacers and recessed thick outer spacers. Another embodiment provides a gate electrode structure with thin inner spacers and partially recessed outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with thin inner spacers and thin outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with recessed thin inner spacers and recessed thin outer spacers.

Device with recessed thin and thick spacers for improved salicide resistance on polysilicon gates

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Beaverton, OR, United States of America

Steven J Keating