Texas Instruments Corporation

Steven J Easley

George L Brantingham

An integrated chip microprocessor system has a data memory for storing numeric data, an arithmetic unit for performing arithmetic operations on such data, an instruction memory for storing a plurality of instruction words, a program counter for addressing the instruction memory, and an instruction word decoder for decoding instruction words outputted from the instruction memory for controlling the operation of the microprocessor system. The instruction word decoder has a branch decoder system for implementing a two cycle branch logic. Each program branch operation, as stored in the instruction memory has two parts: a branch instruction word which indicates a program branch and also indicates the state of a selected one of a plurality of flag latches upon which it is conditioned; and a branch address instruction word solely indicative of the instruction memory address to which the program is to branch, the branch address instruction word being stored in the next memory location in the instruction memory following the branch instruction word. The branch decoder system determines when a branch instruction word is outputted from the instruction memory and also determines if the program branch is conditional or unconditional, and if the branch is conditional, the particular state of a selected flag latch upon which the branch is conditioned. If the branch is unconditioned, or if the branch is conditional and the condition satisfied, the branch decoder system inserts the branch address instruction word which is the next instruction word outputted from the instruction memory into the program counter.

Electronic microprocessor system having two cycle branch logic

An electronic calculator or microprocessor system having a selectively loadable instruction register is disclosed. The system preferably includes a data memory for storing numeric data, an arithmetic unit for performing arithmetic operations on the data stored in the data memory, an instruction memory for storing a plurality of instruction words, the instruction words controlling the operation of the system, and a program counter for addressing the instruction memory. The system is provided with a selectively loadable instruction register for temporarily storing the instruction word outputted from the instruction memory when enabled by an enabling signal. The enabling signal is provided by a first decoder logic circuit responsive to at least a portion of each instruction word outputted from the instruction memory for generating the enabling signal for a selected ones of the plurality instruction words. The system is further provided with second and third decoder logic circuits for decoding the instruction words loaded into the instruction word register and decoding the instruction words as outputted from the instruction memory, respectively. The first decoder logic circuit is preferably arranged to generate the enabling signal for loading the instruction word into the instruction word register for all instructions except BRANCH, CALL, RETURN, and DONE instructions, for instance. Preferably then when the instruction word register is not loaded with an instruction from the instruction memory because of the lack of an enabling signal, the instruction word register is preferably loaded with a no-operation instruction, the no-operation instruction permitting data to be maintained in the system's data memory.

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Houston, TX, United States of America

Steven J Easley