Analog Devices,inc.

Steven J Decker

Shrenik Deliwala

Katsufumi Nakamura

Dan M Weinberg

Stuart D Boyd

Laurier St Onge

Isaac Chase Novet

Gregory T Koker

Katsu Nakamura

Lawrence A Singer

David Paul Foley

Edward Chapin Guthrie

Jianrong Chen

Stephen Robert Kosic

Daniel F Kelly

Mark T Sayuk

Masatoshi Sase

David P Foley

An impedance sensing circuit includes three impedance elements and a sensing element arranged in a bridge configuration. A first input terminal is coupled to two of the impedance elements to apply a stimulus signal. In a mutual-sensing mode, a second input terminal is coupled to the third impedance element and the sensing impedance element to apply an opposite phase stimulus signal. The impedance sensing circuit may be configured in a self-sensing mode, in which the opposite phase stimulus signal is decoupled from the third impedance element and the sensing impedance element. At least one of the impedance elements is variable and may be adjusted to balance an offset impedance load on the sensing element.

Bridge-based impedance sensor system

A current detection module capable of differentiating and quantifying contribution to a current signal generated by a sensor in response to stimulation by a certain target source from contributions from sources other than the target source (ambient sources) is disclosed. As long as the contribution from the target source comprises a pulsed signal, the module may synchronize itself to the pulse(s) so that there is a predetermined phase relationship between the pulse(s) and functions carried out by various stages of the module. The module may be re-used to also detect and quantify contributions from ambient sources by presenting these contributions to the module as pulses that trigger synchronization of the module. To that end, a detection system disclosed herein is based on the use of such current detection module and allows mode switching where, depending on the selected mode of operation, the module is configured to perform different measurements.

Circuit architecture for mode switch

An electrical circuit includes a sensor configured to generate a current signal comprising a first portion comprising a contribution from a target source and/or a second portion comprising a contribution from sources other than the target source, a trans-impedance amplifier that amplifies the current signal and generate a low noise signal, and a high pass filter that converts the low noise signal into an AC signal having a positive amplitude, a negative amplitude, and a zero cross-over point between the positive and negative amplitudes. The circuit also includes a positive integrating amplifier that receives the positive amplitude of the AC signal and generates a positive integrated value over an integration period, and a negative integrating amplifier that receives the negative amplitude of the AC signal and generates a negative integrated value over the integration period. The circuit further includes at least one analog-to-digital converter that receives the integrated values.

Four-stage circuit architecture for detecting pulsed signals

An electrical circuit includes a photodiode that receives a light signal from a light source and generates a photocurrent signal, a trans-impedance amplifier that amplifies the photocurrent signal and generates a low noise signal, and a high pass filter that converts the low noise signal into an alternating current (AC) signal having a positive amplitude, a negative amplitude, and a zero cross-over point between the positive amplitude and the negative amplitude. The electrical circuit also includes a positive integrating amplifier that receives the positive amplitude of the AC signal and generates a positive integrated value over an integration period, and a negative integrating amplifier that receives the negative amplitude of the AC signal and generates a negative integrated value over the integration period. The electrical circuit further includes at least one analog-to-digital converter that receives the positive and negative integrated values.

Previously available analog domain decimation techniques are limited to simple equally-weighted averaging of photosite outputs. Decimation of a Bayer pattern image by an even-factor, such as by two or six, using simple equally-weighted averaging of photosite outputs in the analog domain results in effective sampling locations that are unevenly spaced apart. Standard interpolation of the unevenly spaced effective sampling locations generates image artifacts that reduce the quality of the reconstructed image in the smaller format because standard interpolation methods assume that the effective sampling locations are evenly spaced. Implementations of systems, methods and apparatus disclosed herein aim to produce substantially evenly spaced effective sampling locations in the analog domain. More specifically, in some implementations, the unequally-weighted-average even-factor decimation methods disclosed herein produce substantially more evenly spaced effective sampling locations as compared to the equally-weighted-average even-factor decimation processes previously used in the analog domain.

Apparatus and method for image decimation for image sensors

A gated-clock shift register including a series of clocked flip-flops with preceding outputs connected to subsequent inputs as a horizontal digital shift register. Each flip-flop (or other state holding device) includes a clock buffer between the respective flip-flop's clock, and the global clock. Each clock buffer propagates the clock signal when it determines the associated flip-flop will have a state change during that clock cycle (e.g., via an XOR of the flip-flops input and output signals). In the absence of a state change, that buffer does not propagate the clock signal, essentially only clocking the relevant flip-flops. Further, the clock buffer may be implemented with only NMOS devices (or alternatively, only PMOS devices), which offers power savings over an otherwise required CMOS implementation.

Clock gated power saving shift register

A differential two-stage Miller compensated amplifier system with capacitive level shifting includes a first stage differential transconductance amplifier including first and second output nodes and an output common mode voltage, a second stage differential transconductance amplifier including non-inverting and inverting inputs and outputs and an input common mode voltage, and a level shifting capacitor circuit coupled between the first and second output nodes and the non-inverting and inverting inputs for level shifting between the output common mode voltage of the first stage and the input common mode voltage of the second stage.

Differential two-stage miller compensated amplifier system with capacitive level shifting

A state machine circuit may be used to control a multiplexing circuit that selects and provides respective ones of multiple input clock signals to a clock-synthesizing circuit that generates a synthesized clock signal in response to such input clock signals. The state machine circuit may, for example, be configured so that the synthesized clock signal is a spread-spectrum clock signal and/or a clock signal having a nominal frequency that is greater than a nominal frequency of each of the input clock signals.

Spread-spectrum clocking

In one embodiment, an image sensor includes an area pixel array, column readout lines, and array readout lines, wherein the area pixel array includes columns of pixels, each including pixels of a first type, each column readout line is selectively coupled to outputs of the pixels of the first type that are included in a respective column of pixels, and each array readout line is selectively coupled to at least one of the first column readout lines. In another embodiment, an image sensor includes a pixel array, column readout lines, and array readout lines, wherein the pixel array includes a row of pixels which includes pixels of a first type, each column readout line is selectively coupled to an output of a respective pixel of the first type that is included in the row of pixels, and each array readout line is selectively coupled to at least one of the column readout lines.

Image sensor using multiple array readout lines

A correlated double sampling pixel gain amplifier includes an operational amplifier, an input sampling capacitor, and a feedback capacitor. The input capacitor samples the input signal during a first time phase and the feedback capacitor receives the signal charge from the input capacitor. No sampling switch is located between the input capacitor and the input terminal. The feedback capacitor may include a capacitor array.

Pixel gain amplifier

One embodiment of the invention is directed to a method comprising an act of performing digital correction of an offset in a system comprising an analog-to-digital converter (ADC) having a usable input range that is greater than a nominal input range, wherein the offset exists at an input of the ADC. Another embodiment of the invention is directed to a system comprising an ADC having a usable input range that is greater than a nominal input range, wherein an offset exists at an input of the ADC and the offset is corrected using digital correction.

Methods and apparatus for digital offset correction using an ADC with an increased input range

One embodiment of the invention is directed to a method of extending the input range of an analog-to-digital converter (ADC) having a nominal input voltage range. The method comprises an act of mapping an over-range input voltage that falls outside of the nominal input voltage range to an over-range digital output code. Another embodiment of the invention is directed to an apparatus comprising an ADC having a nominal input voltage range, wherein the ADC is adapted to map an over-range input voltage that falls outside of the nominal input voltage range to an over-range digital output code.

Analog-to-digital conversion using an increased input range

An offset correction circuit loop with summing nodes, a variable gain transconductance amplifier and capacitor. The input to the loop is sent to a first summing node and then to a separate circuit. The output of the separate circuit is sent to the output of the loop and to the input of a second summing node. The second summing node subtracts the circuit output from a reference voltage and sends the result to the transconductance amplifier which outputs a corrective current which is then integrated onto the capacitor to produce a corrective input offset voltage estimate.

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Sandown, NH, United States of America

Steven J Decker