Silicon Graphics, Incorporated

Steven J Ciavaglia

Joseph P Bratt

Peter Y Hsu

Joseph T Scanlon

Man K Tang

John Brennen

A conflict resolution system for interleaved memories in processors capable of issuing multiple independent memory operations per cycle. The conflict resolution system includes an address bellow for temporarily storing memory requests, and cross-connect switches to variously route multiple parallel memory requests to multiple memory banks. A control logic block controls the address bellow and the cross-connect switches to reorder the sequence of memory requests to avoid conflicts. The reordering removes conflicts and increases the occurrence of alternating memory requests that can issue simultaneously.

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Willinston, VT, United States of America

Steven J Ciavaglia