Globalfoundries Inc.

International Business Machines Corporation

Globalfoundries U.S. Inc.

Renesas Electronics Corporation

Steven J Bentley

Ruilong Xie

Ajey Poovannummoottil Jacob

Julien Frougier

Chanro Park

Puneet Harischandra Suvarna

Murat Kerem Akarvardar

Kwan-Yong Lim

Kangguo Cheng

Daniel Chanemougame

Jody Alan Fronheiser

Steven R Soss

John H Zhang

Hiroaki Niimi

Brent A Anderson

Min Gyu Sung

Bruce Bennett Doris

Ali Khakifirooz

Nicolas J Loubet

Lars W Liebmann

Siva P Adusumilli

Michael Joseph Zierak

Pietro Montanini

Johnatan A Kantarovsky

Toshiharu Nagumo

Rohit Galatage

Tenko Yamashita

Junli Wang

Su Chen Fan

Gerard M Schmid

Bipul C Paul

Bartlomiej Jan Pawlak

Richard Farrell

Hui Zang

Hoon Sik Kim

Ali Razavieh

Carl John Radens

Balasubramanian Pranatharthiharan

Zoran Krivokapic

Rajendran Krishnasamy

Cheng Chi

Santosh Sharma

Chia-Yu Chen

Mark Levy

Deepak K Nayak

Jeonghyun Hwang

Brian Alexander Cohen

Anthony K Stamper

Xin Miao

John J Ellis-Monaghan

Vibhor Jain

Alvin Jose Joseph

Haiting Wang

Hong Yu

Francois Hebert

Guillaume Bouche

Xusheng Kevin Wu

Jiehui Shu

Muthumanickam Sankarapandian

Pierre Morin

Haigou Huang

Vimal Kumar Kamineni

Michael John Hargrove

Yi Qi

Naim Moumen

Ephrem G Gebreselasie

Mark V Raymond

Ramsey M Hazbun

Shurong Liang

Kejia Wang

Ryan O Jung

Nigel Graeme Cave

Romain Lallement

Emilie Bourjot

Sylvie M Mignot

Joseph S Washington

Jiseok Kim

Mira Park

Peter M Zeitzoff

Sivanandha K Kanakasabapathy

Lawrence Selvaraj Susai

Bum Ki Moon

Amitabh Jain

Embodiments of the disclosure provide an electrically programmable fuse (efuse) over crystalline semiconductor material. A structure according to the disclosure includes a plurality of crystalline semiconductor layers. Each crystalline semiconductor layer includes a compound material. A metallic layer is on the plurality of crystalline semiconductor layers. The metallic layer has a lower resistivity than an uppermost layer of the plurality of crystalline semiconductor layers. A pair of gate conductors is on respective portions of the metallic layer. The metallic layer defines an electrically programmable fuse (efuse) link between the gate conductors.

Electrically programmable fuse over crystalline semiconductor materials

A structure includes a negative temperature coefficient (NTC) resistor for use in gallium nitride (GaN) technology. The NTC resistor includes a p-type doped GaN (pGaN) layer, and a gallium nitride (GaN) heterojunction structure under the pGaN layer. The GaN heterojunction structure includes a barrier layer and a channel layer. An isolation region extends across an interface of the barrier layer and the channel layer, and a first metal electrode is on the pGaN layer spaced from a second metal electrode on the pGaN layer. The NTC resistor can be used as a temperature compensated reference in a structure providing a temperature detection circuit. The temperature detection circuit includes an enhancement mode HEMT sharing parts with the NTC resistor and includes temperature independent current sources including depletion mode HEMTs.

Temperature detection using negative temperature coefficient resistor in GaN setting

The present disclosure relates to semiconductor structures and, more particularly, to multi-channel transistors and methods of manufacture. The structure includes: a gate structure; a single channel layer in a channel region under the gate structure; a drift region adjacent to the gate structure; and multiple channel layers in the drift region coupled to the single channel layer under the gate structure.

Multi-channel transistor

The present disclosure relates generally to structures in semiconductor devices and methods of forming the same. More particularly, the present disclosure relates to semiconductor devices having field plates that are arranged symmetrically around a gate. The present disclosure provides a semiconductor device including an active region above a substrate, source and drain electrodes in contact with the active region, a gate above the active region and laterally between the source and drain electrodes, a first field plate between the source electrode and the gate, a second field plate between the drain electrode and the gate, in which the gate is spaced apart laterally and substantially equidistant from the first field plate and the second field plate.

Symmetric arrangement of field plates in semiconductor devices

A semiconductor device is provided, the semiconductor device comprising a substrate having merged cavities in the substrate. An active region is over the merged cavities in the substrate. A thermally conductive layer is in the merged cavities in the substrate, whereby the thermally conductive layer at least partially fills up the merged cavities in the substrate. A first contact pillar connects the thermally conductive layer in the merged cavities in the substrate with a metallization layer above the active region.

Substrate with a buried conductor under an active region for enhanced thermal conductivity and RF shielding

Semiconductor structures including electrical isolation and methods of forming a semiconductor structure including electrical isolation. A layer stack is formed on a semiconductor substrate comprised of a single-crystal semiconductor material. The layer stack includes a semiconductor layer comprised of a III-V compound semiconductor material. A polycrystalline layer is formed in the semiconductor substrate. The polycrystalline layer extends laterally beneath the layer stack.

III-V compound semiconductor layer stacks with electrical isolation provided by a trap-rich layer

A semiconductor device is provided, the semiconductor device comprising a substrate and a first semiconductor fin and a second semiconductor fin disposed over the substrate. The first and second semiconductor fins each having an upper portion and a width. Epitaxial structures are disposed over the upper portions of the first and second semiconductor fins. The upper portions of the first and second semiconductor fins and the epitaxial structures provide an active layer. A metal structure is positioned between the active layer and the substrate. The metal structure extends at least across the widths of the first and second semiconductor fins and a separation distance between the fins. A first isolation material separates the metal structure from the active layer. A second isolation material separates the metal structure from the substrate. A contact electrically connects the metal structure to the epitaxial structures.

Semiconductor device with metal structure under an active layer

A semiconductor device at least one first transistor of a first type disposed above a substrate and comprising a channel wider in one cross-section than tall, wherein the first type is a PFET transistor or an NFET transistor; and at least one second transistor of a second type disposed above the at least one first transistor and comprising a channel taller in the one cross-section than wide, wherein the second type is a PFET transistor or an NFET transistor, and the second type is different from the first type. Methods and systems for forming the semiconductor structure.

Method, apparatus, and system for fin-over-nanosheet complementary field-effect-transistor

An integrated circuit (IC) structure includes a long channel (LC) gate structure over a long channel region, the LC gate structure having a first gate height; and a short channel (SC) gate structure over a short channel region, the SC gate structure having a second gate height. The short channel region is shorter in length than the long channel region. The second gate height of the SC gate structure is no larger than the first gate height of the LC gate structure.

IC structure with short channel gate structure having shorter gate height than long channel gate structure

Methods form devices by creating openings in sacrificial gates between nanosheet stacks (alternating layers of a first material and channel structures), forming spacers in the openings, and removing the sacrificial gates to leave the spacers. The first material is then removed from between the channel structures. A first work function metal is formed around and between the channel structures. Next, first stacks (of the stacks) are protected with a mask to leave second stacks (of the stacks) exposed. Then, the first work function metal is removed from the second stacks while the first stacks are protected by the mask and the spacers. Subsequently, a second work function metal is formed around and between the channel structures of the second stacks. A gate material is then formed over the first work function metal and the second work function metal.

Nanosheet field effect transistor with spacers between sheets

Vertical field effect transistor (VFET) structures and methods of fabrication include a bottom spacer having a uniform thickness. The bottom spacer includes a bilayer portion including a first layer formed of an oxide, for example, and a second layer formed of a nitride, for example, on the first layer, and a monolayer portion of a fourth layer of a nitride for example, immediately adjacent to and intermediate the fin and the bilayer portion.

Uniform bottom spacer for VFET devices

Embodiments of the invention are directed to a method and resulting structures for a semiconductor device having self-aligned contacts. In a non-limiting embodiment of the invention, a semiconductor fin is formed vertically extending from a bottom source/drain region of a substrate. A conductive gate is formed over a channel region of the semiconductor fin. A top source/drain region is formed on a surface of the semiconductor fin and a top metallization layer is formed on the top source/drain region. A dielectric cap is formed over the top metallization layer.

Self-aligned contact for vertical field effect transistor

Methods of forming contacts for vertical-transport field-effect transistors and structures for a vertical-transport field-effect transistor and contact. An interlayer dielectric layer is deposited over a gate stack, and a first opening is formed in the interlayer dielectric layer and penetrates through the gate stack to cut the gate stack into a first section and a second section. A dielectric pillar is formed in the first opening and is arranged between the first section of the gate stack and the second section of the gate stack. Second and third openings are formed in the interlayer dielectric layer that penetrate to the gate stack and that are divided by the dielectric pillar. A first contact in the second opening is coupled with the first section of the gate stack, and a second contact in the third opening is coupled with the second section of the gate stack.

Vertical-transport field-effect transistors with self-aligned contacts

Fabricating a feedback field effect transistor includes receiving a semiconductor structure including a substrate, a first source/drain disposed on the substrate, a fin disposed on the first source/drain, and a hard mask disposed on a top surface of the fin. A bottom spacer is formed on a portion of the first source/drain. A first gate is formed upon the bottom spacer. A sacrificial spacer is formed upon the first gate, a gate spacer is formed on the first gate from the sacrificial spacer, and a second gate is formed on the gate spacer. The gate spacer is disposed between the first gate and the second gate. A top spacer is formed around portions of the second gate and hard mask, a recess is formed in the top spacer and hard mask, and a second source/drain is formed in the recess.

Sub-thermal switching slope vertical field effect transistor with dual-gate feedback loop mechanism

Growing community of inventors

Menards, NY, United States of America

Steven J Bentley