National Semiconductor Corporation

Texas Instruments Corporation

National Semiconductor Corporated

Steven J Adler

Peter B Johnson

Ira Oaktree Wygant

Mingwei Xu

Yaojian Leng

Abbas Ali

Rajni J Aggarwal

Shahram Mostafazadeh

Jamal Ramdani

Richard Wendell Foote, Jr

Eugene C Davis

Andre Paul Labonte

Craig Richard Printy

Gokhan Percin

Todd Patrick Thibeault

Heather McCulloh

Henry G Prosack, Jr

Scott David Ruby

Patrick McCarthy

Richard Foote

An integrated circuit includes a bipolar transistor extending into a [100] surface of a semiconductor substrate having a crystalline lattice. A deep trench surrounds the bipolar transistor and has a path having a plurality of sides. At least one side extends in a direction parallel to a <100> axis of the crystalline lattice.

Reduced silicon dislocation defects from deep SI trench integration

An electronic device comprises a semiconductor substrate including majority carrier dopants of a first conductivity type, a semiconductor surface layer including majority carrier dopants of a second conductivity type, field oxide that extends on the semiconductor surface layer, and an isolation structure. The isolation structure includes a trench that extends through the semiconductor surface layer and into one of the semiconductor substrate and a buried layer of the semiconductor substrate, and polysilicon including majority carrier dopants of the second conductivity type, the polysilicon fills the trench to a side of the semiconductor surface layer.

Deep trench isolation with field oxide

A trench DMOS transistor with a very low on-state drain-to-source resistance and a high gate-to-drain charge includes one or more floating islands that lie between the gate and drain to reduce the charge coupling between the gate and drain, and effectively lower the gate-to-drain capacitance.

Trench DMOS transistor with reduced gate-to-drain capacitance

A capacitive micromachined ultrasonic transducer (CMUT), which has a conductive structure that can vibrate over a cavity, has a number of vent holes that are formed in the bottom surface of the cavity. The vent holes eliminate the deflection of the CMUT membrane due to atmospheric pressure which, in turn, allows the CMUT to receive and transmit low frequency ultrasonic waves.

Low frequency CMUT with vent holes

A method for forming a capacitive micromachined ultrasonic transducer (CMUT) includes forming multiple CMUT elements in a first semiconductor-on-insulator (SOI) structure. Each CMUT element includes multiple CMUT cells. The first SOI structure includes a first handle wafer, a first buried layer, and a first active layer. The method also includes forming a membrane over the CMUT elements and forming electrical contacts through the first handle wafer and the first buried layer. The electrical contacts are in electrical connection with the CMUT elements. The membrane could be formed by bonding a second SOI structure to the first SOI structure, where the second SOI structure includes a second handle wafer, a second buried layer, and a second active layer. The second handle wafer and the second buried layer can be removed, and the membrane includes the second active layer.

Integration of structurally-stable isolated capacitive micromachined ultrasonic transducer (CMUT) array cells and array elements

A high-frequency capacitive micromachined ultrasonic transducer (CMUT) has a silicon membrane and an overlying metal silicide layer that together form a conductive structure which can vibrate over a cavity. The CMUT also has a metal structure that touches a group of conductive structures. The metal structure has an opening that extends completely through the metal structure to expose the conductive structure.

High frequency CMUT

A capacitive micromachined ultrasonic transducer (CMUT), which has a conductive structure that can vibrate over a cavity, utilizes a thick oxide layer to substantially increase the volume of the cavity which, in turn, allows the CMUT to receive and transmit low frequency ultrasonic waves. In addition, the CMUT can include a back side bond pad structure that eliminates the need for and cost of one patterned photoresist layer.

Low frequency CMUT with thick oxide

A method includes forming first isolation trenches in a first side of a first semiconductor-on-insulator (SOI) structure to electrically isolate multiple portions of the first SOI structure from each other. The method also includes bonding a second SOI structure to the first SOI structure to form multiple cavities between the SOI structures. The method further includes forming conductive plugs through a second side of the first SOI structure and forming second isolation trenches in the second side of the first SOI structure around the conductive plugs. In addition, the method includes removing portions of the second SOI structure to leave a membrane bonded to the first SOI structure. The isolated portions of the first SOI structure, the cavities, and the membrane form multiple capacitive micromachined ultrasonic transducer (CMUT) elements. Each CMUT element is formed in one of the isolated portions of the first SOI structure and includes multiple CMUT cells.

Method of forming a capacitive micromachined ultrasonic transducer (CMUT)

A system and method are disclosed for providing a self aligned bipolar transistor using a silicon nitride ring. An active region of the transistor is formed and a sacrificial emitter is formed above the active region of the transistor. A silicon nitride ring is formed around the sacrificial emitter. The sacrificial emitter and the silicon nitride ring are formed by depositing a layer of silicon nitride material over the active area of the transistor and performing an etch process to simultaneously create both the sacrificial emitter and the silicon nitride ring. The silicon nitride ring provides support for forming a raised external base for the transistor.

System and method for providing a self aligned bipolar transistor using a silicon nitride ring

A system and method are disclosed for providing a self aligned bipolar transistor using a simplified sacrificial nitride emitter. An active region of a transistor is formed and a silicon nitride sacrificial emitter is formed above the active region of the transistor. Then a physical vapor deposition oxide layer is deposited over the silicon nitride sacrificial emitter using a physical vapor deposition process. The physical vapor deposition oxide layer is then etched away from the side walls of the sacrificial emitter. The sacrificial emitter is then etched away to form an emitter window. Then a polysilicon emitter structure is formed in the emitter window. The self aligned bipolar transistor architecture of the invention is compatible with BiCMOS technology.

System and method for providing a self aligned bipolar transistor using a simplified sacrificial nitride emitter

An electronic apparatus is disclosed that comprises a silicon nitride material that has an increased silicon content. The silicon nitride material is manufactured by exposing plasma enhanced chemical vapor deposition (PECVD) silicon nitride to an increased flow of silane while the PECVD silicon nitride is being deposited. The material has anti-reflective coating (ARC) properties and can also be used as a hard mask. When the material is covered with cobalt the material forms conductive cobalt silicide when the cobalt is annealed. A method for siliciding the PECVD silicon nitride is also disclosed.

System and method for using siliciding PECVD silicon nitride as a dielectric anti-reflective coating and hard mask

A system and method is disclosed for manufacturing a bipolar junction transistor that comprises an emitter/base layer that is formed by a single deposition process. In one advantageous embodiment of the invention the emitter/base layer comprises an emitter layer that comprises an epitaxially grown mono-silicon emitter. The epitaxially grown mono-silicon emitter significantly reduces the electrical resistivity of the emitter. A non-dopant impurity such as germanium is added to the base layer to endpoint a dry plasma etch process that is applied to etch the emitter/base layer.

System and method for providing a single deposition emitter/base in a bipolar junction transistor

A system and method are disclosed for manufacturing an emitter structure in a complementary bipolar complementary metal oxide semiconductor (CBiCMOS) transistor manufacturing process. A protective layer is formed over an emitter layer in a transistor structure and lateral portions of the protective layer and the emitter layer are etched to form an emitter structure. An oxide layer is then deposited over the transistor structure and an etchback process is performed to remove portions of the oxide layer from the top of the protective layer. A source/drain implant process is then performed to implant an extrinsic base region of the transistor. The protective layer protects the emitter structure from the implant process. Then the protective layer is removed from the emitter structure.

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Saratoga, CA, United States of America

Steven J Adler