Forza Silicon Corporation

Other

Sunplus Technology Co., Ltd.

Steven Huang

Daniel A Van Blerkom

Barmak Mansoorian

Loc Truong

Te-Sung Su

Lin Ping Ang

I-Shiou Chen

Dexue Zhang

Jonathan Bergey

Sam Bagwell

Ramy Tantawy

Ali Mesgarani

Christophe Ca Basset

Jack Zheng

Yingying Wang

Rami Tantawy

Disclosed herein are novel charge mode readout circuits and associated methods of signal processing. The devices and methods of the invention allow for the improved processing of stored signals by a charge mode readout amplifier, wherein the readout level may be shifted to a desired range and wherein a fully differential output swing may be imparted. The invention advantageously employs a single pair of capacitors to serve the dual roles of modulating amplifier gain and level shifting the output.

Fully differential output swing for analog array based charge mode readout used in a CMOS image sensor

Ping-pong readout architecture allows for faster frame rates in CMOS image sensors. However, various problems are created by this architecture due to cross-talk between components. Provided herein are novel ping-pong readout layouts which better isolate components to reduce crosstalk issues. Also provided herein are novel timing schemes for operating ping-pong readout circuits which prevent crosstalk signal spikes or readout corruption.

Layout and timing schemes for ping-pong readout architecture

A stitched image sensor array on a semiconductor substrate with identical blocks that have wherein said first configuration includes enable inputs, which vary a function of the block depending on the connection to the enable inputs. The enable inputs can set an SRAM to receive different numbers of inputs.

Method for reading out multiple SRAM blocks with different column sizing in stitched CMOS image senor

Methods and systems for analog-to-digital conversion applicable to an image sensor, such as a CMOS image sensor, in which an ADC comprises built-in redundancy such that the ADC can start its conversion cycle before the ADC input settles to a desired resolution and the ADC can yet accurately convert the ADC input to a digital value with the desired resolution. In a CMOS image sensor, such an ADC configuration enables the pixel readout time to overlap with the ADC conversion time, reducing the total time needed to convert the pixel signal value to a digital value with the desired resolution.

Analog-to-digital converter with redundancy for image sensor readout

An image sensor array that has a plurality of image sensing pixels and a plurality of programmable gain amplifiers, each of the programmable gain amplifiers connected to receive and amplify an output of said image sensing pixels. Each of said programmable gain senses when an output of the programmable gain amplifier is in an oversaturated condition. Responsive to sensing that the output of the programmable gain amplifier in the oversaturated condition, the amplifier automatically clamps a bias amount to the programmable gain amplifier, to thereby regulate an amount of current draw of the programmable gain amplifier. In this way, the power supply current to that pixel which is oversaturated is prevented from affecting power supplies to the other pixels, by regulating the power supply to the oversaturated pixel.

Power supply regulation for programmable gain amplifier used in a CMOS image sensor

Methods and systems for analog-to-digital conversion applicable to an image sensor, such as a CMOS image sensor, in which pixels can be readout non-destructively, and wherein a non-destructive pixel read may be used to provide a coarse analog-to-digital conversion such that information can be stored, and the stored information is then applied in a fine analog-to-digital conversion during a subsequent actual pixel read.

Analog-to-digital conversion for image sensor with non-destructive read pixel

An A/D converter system that has a ranging detector that receives and characterizes an input signal. The characterizing sets a coarse range selection based on a level of the input signal. A higher level input signal has a higher level ranging. An A/D converter includes a compression system that compresses based on the ranging output signal by converting different numbers of bits for different level ranging output signal. A higher level input signal is more higher compressed and produces a digital output indicative of the input signal, which is compressed by different amounts based on the ranging output signal. By scaling in this way, the resolution of the A/D converter is scaled on the basis of shot noise level of the image sensor.

Analog to digital converter with built-in data compression based on shot noise of image sensor

A successive approximation A/D converter which includes a sub ranging classifier that receives an input signal and classifies said input signal according to plural different highest resolution bits, to determine a range of the input signal, and creating a set of most significant bits based on said range, said subranging classifier also setting and determining an offset based on said range, and a successive approximation A/D converted that converting lowest resolution parts of the input signal as adjusted by the offset.

Segmented column-parallel analog-to-digital converter

A chip device with a number of individually powered parts, such as photoreceptors. A mesh is provided to provide power to the individual photoreceptors. The mesh may be provided for ground and power and/or both. The mesh may be on different layers, so that one portion of the mesh is exactly over the other portion of the mesh. The mesh takes up a portion of real estate on the chip in between the individual photoreceptors, in locations where image sensing parts cannot be located. In an embodiment, the mesh can be intentionally broken at various locations to optimize the path length.

Power grid abutting a photoreceptor element and having a break in a geometric location to shift power flow of the grid

Ground and power mesh in an integrated circuit chip

A column parallel image sensor such as an active pixel sensor includes a calibration circuit for the readout circuit within the active pixel sensor. The calibration circuit produces a value that is stored and used to offset any noise in the A/D converter. The calibration is carried out each time that each row is read out so in effect the calibration's individual for each pixel. Hence, any noise within the calibration evens out within the image, and is effectively random within the image and hence becomes less noticeable within the image.

Individual row calibration in an image sensor

A circuit and method thereof for sampling/holding signal is provided. The signal sampling/holding circuit comprises a first signal sampling/holding device, a second signal sampling/holding device, a target signal and a reference voltage. First, the first signal sampling/holding device is supplied with the reference voltage and the target signal. The reference voltage is disconnected from the first signal sampling/holding device before the target signal is. Similarly, the reference voltage is disconnected from the second signal sampling/holding device before the target signal is. Thus the target signal is respectively sampled and held in the first signal sampling/holding device and the second signal sampling/holding device.

Method and circuit for sampling/holding a signal

A frame shuttered CMOS image sensor with simultaneous array readout. An array of CMOS pixels are printed on a silicon substrate. Within each pixel is a light sensitive region comprising a photo sensitive diode for converting photons into electrical charge and at least three transistors to permit reading of reset electrical charges and collected electrical charges and for re-setting the photosensitive diode. The sensor includes an array of signal and re-set readout capacitors located on the substrate but outside of the pixel array. Metal conductors printed in said substrate connect each pixel in said pixel array with a signal capacitor and a re-set capacitor in array of signal and re-set readout capacitors. Transistor switches printed in said substrate but outside of said pixel array are used to isolate the signal and re-set capacitors from each other and from the pixels. Control circuitry is provided for re-setting simultaneously each of the pixels in the pixel array, for collecting simultaneously re-set signals from each pixel on to one of the reset capacitors in the array of readout capacitors and for collecting simultaneously integrated pixel signals from each pixel on to one of the signal capacitors in the array of readout capacitors. Readout circuitry is provided for reading charges collected on the array of signal and re-set capacitors.

Frame-shuttered CMOS image sensor with simultaneous array readout

A common operational amplifier for a pipeline circuit is provided. The common operational amplifier is used by the stage circuits of the pipeline circuit by turns according to a predetermined timing. The common operational amplifier comprises an operational amplifier circuit, a multiplexer circuit and a demultiplexer circuit. The multiplexer circuit is provided for selecting a signal set of a stage circuit to be amplified to couple to the operational amplifier circuit, and the demultiplexer circuit is provided for transmitting the amplified signal set to the corresponding stage circuit.

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Pasadena, CA, United States of America

Steven Huang