Intel Corporation

Steven Hsu

Ram K Krishnamurthy

Amit Agarwal

Simeon Realov

Sanu K Mathew

Vivek K De

Mark A Anders

Iqbal Rajwani

Satish K Damaraju

Bhaskar P Chatterjee

Shih-Lien L Lu

Atul Maheshwari

Chris Hyung-il Kim

Mahesh K Kumashikar

Monodeep Kar

Dinesh Somasekhar

Stephen H Tang

Gautham N Chinya

Himanshu Kaul

Sriram R Vangal

Atila Alvandpour

Anupama Ambardar Thaploo

Arnab Raha

Debabrata Mohapatra

Martin Power

Feroze Merchant

Sri Harsha Choday

Vinod Sannareddy

Gian Gerosa

Moongon Jung

Vishak Venkatraman

Daniel I Davis

Deepak Abraham Mathaikutty

Raymond Jit-Hung Sung

David Thomas Bernard

Conor Byrne

Systems, apparatuses and methods identify a plurality of registers that are associated with a system-on-chip. The plurality of registers includes a first portion dedicated to write operations and a second portion dedicated to read operations. The technology writes data to the first portion of the plurality of registers, and transfers the data from the first portion to the second portion.

Multi-buffered register files with shared access circuits

A method comprising: dividing a 3D space into a voxel grid comprising a plurality of voxels; associating a plurality of distance values with the plurality of voxels, each distance value based on a distance to a boundary of an object; selecting an approximate interpolation mode for stepping a ray through a first one or more voxels of the 3D space responsive to the first one or more voxels having distance values greater than a threshold; and detecting the ray reaching a second one or more voxels having distance values less than the first threshold; and responsively selecting a precise interpolation mode for stepping the ray through the second one or more voxels.

Apparatus and method for approximate trilinear interpolation for scene reconstruction

A parasitic-aware single-edge triggered flip-flop reduces clock power through layout optimization, enabled through process-circuit co-optimization. The static pass-gate master-slave flip-flop utilizes novel layout optimization enabling significant power reduction. The layout removes the clock poly over notches in the diffusion area. Poly lines implement clock nodes. The poly lines are aligned between n-type and p-type active regions.

Low power flip-flop with reduced parasitic capacitance

A fast Mux-D scan flip-flop is provided, which bypasses a scan multiplexer to a master keeper side path, removing delay overhead of a traditional Mux-D scan topology. The design is compatible with simple scan methodology of Mux-D scan, while preserving smaller area and small number of inputs/outputs. Since scan Mux is not in the forward critical path, circuit topology has similar high performance as level-sensitive scan flip-flop and can be easily converted into bare pass-gate version. The new fast Mux-D scan flip-flop combines the advantages of the conventional LSSD and Mux-D scan flip-flop, without the disadvantages of each.

High performance fast Mux-D scan flip-flop

An apparatus is provided which comprises: a multi-bit quad latch with an internally coupled level sensitive scan circuitry; and a combinational logic coupled to an output of the multi-bit quad latch. Another apparatus is provided which comprises: a plurality of sequential logic circuitries; and a clocking circuitry comprising inverters, wherein the clocking circuitry is shared by the plurality of sequential logic circuitries.

Multibit vectored sequential with scan

A new family of shared clock single-edge triggered flip-flops that reduces a number of internal clock devices from 8 to 6 devices to reduce clock power. The static pass-gate master-slave flip-flop has no performance penalty compared to the flip-flops with 8 clock devices thus enabling significant power reduction. The flip-flop intelligently maintains the same polarity between the master and slave stages which enables the sharing of the master tristate and slave state feedback clock devices without risk of charge sharing across all combinations of clock and data toggling. Because of this, the state of the flip-flop remains undisturbed, and is robust across charge sharing noise. A multi-bit time borrowing internal stitched flip-flop is also described, which enables internal stitching of scan in a high performance time-borrowing flip-flop without incurring increase in layout area.

Low-power single-edge triggered flip-flop, and time borrowing internally stitched flip-flop

A family of novel, low power, min-drive strength, double-edge triggered (DET) input data multiplexer (Mux-D) scan flip-flop (FF) is provided. The flip-flop takes the advantage of no state node in the slave to remove data inverters in a traditional DET FF to save power, without affecting the flip-flop functionality under coupling/glitch scenarios.

Double edge triggered Mux-D scan flip-flop

An apparatus is provided which comprises: a first flip-flop (FF) cell with a data path multiplexed with a scan-data path, wherein the scan-data path is independent of a min-delay buffer, wherein the first FF cell has a memory element formed of at least two inverting cells, wherein the two inverting cells are coupled together via a common node; and a second FF cell with a data path multiplexed with a scan-data path, wherein the scan-data path of the second FF cell is independent of a min-delay buffer, and wherein the scan-data path of the second FF cell is coupled to the common node of the first FF cell.

Vectored flip-flop

Some embodiments include apparatus and methods using an input stage and an output stage of a circuit. The input stage operates to receive an input signal and a clock signal and to provide an internal signal at an internal node based at least in part on the input signal. The input signal has levels in a first voltage range. The internal signal has levels in a second voltage range greater than the first voltage range. The output stage operates to receive the internal signal, the clock signal, and an additional signal generated based on the input signal. The output stage provides an output signal based at least in part on the input signal and the additional signal. The output signal has a third voltage range greater than the first voltage range.

Fused voltage level shifting latch

An apparatus is provided which comprises: a first inverter to receive a clock; a pass-gate coupled to the first inverter; a second inverter coupled to the pass-gate and to provide an output clock; and a device coupled to the second inverter and the pass-gate, wherein the transistor and the pass-gate are controllable by a logic that depends on logic values of at least two signals (e.g., an enable and the clock).

Low-power clock gate circuit

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Lake Oswego, OR, United States of America

Steven Hsu