Cypress Semiconductor Corporation

Steven Hedayati

Krishnaswamy Ramkumar

William W C Koutny, Jr

Yitzhak Gilboa

A method is provided for eliminating a polish stop layer from a polishing process. In particular, a method is provided which may include polishing an upper layer of a semiconductor topography to form an upper surface at an elevation above an underlying layer, wherein the upper surface does not include a polish stop material. Preferably, the upper surface of the topography formed by polishing is spaced sufficiently above the underlying layer to avoid polishing the underlying layer. The entirety of the upper surface may be simultaneously etched to expose the underlying layer. In an embodiment, the underlying layer may comprise a lateral variation in polish characteristics. The method may include using fixed abrasive polishing of a dielectric layer for reducing a required thickness of an additional layer underlying the dielectric layer. Such a method may be useful when exposing an underlying layer is desirable by techniques other than polishing.

Method of making a planarized semiconductor structure

A method is provided which includes planarizing structures and/or layers such that step heights of reduced and more uniform thicknesses may be formed. In particular, a method is provided which includes polishing an upper layer of a topography to expose a first underlying layer and etching away remaining portions of the first underlying layer to expose a second underlying layer. The topography may then be subsequently planarized. As such, a method for fabricating shallow trench isolation regions may include forming one or more trenches extending through a stack arranged over a semiconductor substrate. Such a method may further include blanket depositing a dielectric over the trenches and the stack of layers such that the trenches are filled by the dielectric. The dielectric may then be planarized such that upper surfaces of the dielectric remaining within the trenches are coplanar with an upper surface of an adjacent layer of the stack.

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Steven Hedayati