International Business Machines Corporation

Globalfoundries Inc.

Steven Harley Lamphier

Harold Pilo

John Atkinson Fifield

George Maria Braceras

Darren Lane Anand

Eric D Hunt-Schroeder

Vinod Ramadurai

Robert Maurice Houle

Fred John Towler

Geordie M Braceras

John E Barwin, Iii

Ronald DeSales Rossi

Roger Andrew Verhelst

Michael J Schneiderwind

Kevin George Petrunich

Paul Stafford Zerr

The present disclosure relates to a method of a non-volatile one time programmable memory (OTPM) including parallel programming of all banks of the OTPM by programming two rows per bank at a time, verifying the programming by comparing a first row of the two rows per bank, and verifying the programming by comparing a second row of the two rows per bank.

Parallel programming of one time programmable memory array for reduced test time

An approach for providing fine granularity power gating of a memory array is described. In one embodiment, power supply lines are disposed in a horizontal dimension of the memory array parallel to the word lines that access cells arranged in rows and columns of the array, wherein each of the supply lines are shared by adjacent cells in the memory. Power supply lines that activate a row selected by one of the word lines are supplied a full-power voltage value and power supply lines that activate rows adjacent to the selected row are supplied a half-power voltage value, while the power supply lines of the remaining rows in the memory array are supplied a power-gated voltage value.

Fine granularity power gating

A system for integrating dynamic leakage reduction with a write-assisted SRAM architecture includes power line selection circuitry associated with each column of one or more SRAM sub arrays, controlled by a selection signal that selects the associated sub array for a read or write operation, and by a column write signal that selects one of the columns of the sub arrays. The power line selection circuitry locally converts a first voltage, corresponding to a cell supply voltage for a read operation, to a second lower voltage to be supplied to each cell selected for a write operation, as to facilitate a write function. The power line selection circuitry also locally converts the first voltage to a third voltage to be supplied to power lines in unselected sub arrays, the third voltage also being lower than the first voltage so as to facilitate dynamic leakage reduction.

System and method for integrating dynamic leakage reduction with write-assisted SRAM architecture

Disclosed are embodiments of an apparatus incorporating a detection circuit adapted for determining the state of selected fuses and a programming circuit for blowing selected fuses on demand. Also, disclosed are embodiments of an associated method. The detection circuit comprises a plurality of fuses in identical signal and reference legs in order to increase the signal margin for detecting blown fuses and/or current sources configured to pass offset currents through the signal and reference legs in order to set the trip point for detecting blown fuses between the un-blown and the minimum blown resistances. Thus, the invention provides the flexibility of single-sided fuse state detection devices with even greater sensitivity than both single-sided and differential fuse state detection device.

Method of improving fuse state detection and yield in semiconductor applications

A low-voltage differential amplifier circuit is disclosed. The low-voltage differential amplifier circuit includes a first differential amplifier, a second differential amplifier and a summing circuit. The first differential amplifier receives a pair of differential input signals to generate a first output. The second differential amplifier receives the same pair of differential input signals to generate a second output. The summing circuit sums the first output of the first differential amplifier and the second output of the second differential amplifier to provide a common output.

Low-voltage differential amplifier

A SRAM module provides programmability of AC timings such that an end user can adjust or &ldquo;tweak&rdquo; the AC timings to maximize system performance. A variable delay circuit is placed in the path between a signal (e.g., data signal or address signal)and the SRAM set-up and hold register which allows the user to shift the setup-and-hold window by selected increments. The delay circuit can either advance or retard the AC timings. A delay program controlling the delay circuit is selected in one of two ways; either by a default AC timing program stored in a ROM device and preset by the manufacturer, or by a private JTAG instruction and AC programming data input by the user through the JTAG state machine provided on the SRAM chip. Once the optimum delay (or advance) is selected to optimize the SRAM to the cache system this user program may be permanently burned into the default ROM such that the optimum timings are used thereafter as the default.

Memory having user programmable AC timings

An output driver circuit is disclosed that generates an accurate and predictable output impedance driver value corresponding to a programmable external impedance. The output driver circuit includes an external resistance device, voltage comparator device, control logic, an evaluate circuit and off-chip driver (OCD) circuit. Voltage from the external resistance device (VZQ) is compared with voltage created from the evaluate circuit (VEVAL) by the voltage comparator device, which indicates to the control logic whether VEVAL is greater than or less than VZQ. The control logic will adjust the evaluate circuit accordingly with a count until the two voltages are basically equal (i.e., the count is alternating between two adjacent binary count values). At which time the control logic operates the OCD with the lower of the two adjacent count values to produce a proper and predictable driving impedance.

Programmable impedance output driver

Circuit and method are presented for activating/deactivating a special operational mode at power-on of an integrated circuit device having no industry defined test state and/or dedicated test pin. The operational mode is enabled upon powering on the integrated circuit combined with detection of a predefined pattern of a first logic state and a second logic state clocked in successive cycles within a first standard input signal, such as an output enable signal, for a normal operating mode of the device. Special non-functional processing is then performed, such as reading prestored identification data from the integrated circuit and/or testing the integrated circuit via embedded test circuitry including boundary scan or other diagnostic circuitry. This special operational mode is deactivated upon receipt at the integrated circuit device of a second standard input signal, such as a write signal for a random access memory (RAM) device, of a predefined logic state (e.g., write enable state). Deactivating of the special operating mode is transparent to the normal response of the integrated circuit device to the second standard input signal.

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St. Albans, VT, United States of America

Steven Harley Lamphier