Qualcomm Incorporated

Steven Halter

Bohuslav Rychlik

Jeffrey Alexander Levin

Matthew Levi Severson

Jaya Prakash Subramaniam Ganasan

Dipti Ranjan Pal

Girish Bhat

Sudeep Ravi Kottilingal

Jason Edward Podaima

Simon Peter William Booth

Samar Asbe

Paul Christopher John Wiercienski

Cristian Duroiu

Mahadevamurty Nemani

Sina Dena

Manokanthan Somasundaram

Gary Arthur Ciambella

Myil Ramkumar

Daniel R Kindred

Christophe Denis Bernard Avoinne

Miguel Ballesteros

Kangmin Lee

Resource access control in a system-on-chip ('SoC') may employ an agent executing on a processor of the SoC and a trust management engine of the SoC. The agent, such as, for example, a high-level operating system or a hypervisor, may be configured to allocate a resource comprising a memory region to an access domain and to load a software image associated with the access domain into the memory region. The trust management engine may be configured to lock the resource against access by any entity other than the access domain, to authenticate the software image associated with the access domain, and to initiate booting of the access domain in response to a successful authentication of the software image associated with the access domain.

Access control system and method for isolating mutually distrusting security domains

In some aspects, the present disclosure provides a method for bandgap voting. In some configurations, the method includes receiving: (i) a first set of votes from a first client of a system, and (ii) a second set of votes from a second client of the system, wherein the first set of votes indicate a first desired set of operational parameters for controlling a plurality of physical resources in the system, wherein the second set of votes indicate a second desired set of operational parameters for controlling the plurality of physical resources, and wherein the plurality of physical resources are shared by the first client and the second client.

System state management

Methods and systems are disclosed for full-hardware management of power and clock domains related to a distributed virtual memory (DVM) network. An aspect includes transmitting, from a DVM initiator to a DVM network, a DVM operation, broadcasting, by the DVM network to a plurality of DVM targets, the DVM operation, and, based on the DVM operation being broadcasted to the plurality of DVM targets by the DVM network, performing one or more hardware optimizations comprising: turning on a clock domain coupled to the DVM network or a DVM target of the plurality of DVM targets that is a target of the DVM operation, increasing a frequency of the clock domain, turning on a power domain coupled to the DVM target based on the power domain being turned off, or terminating the DVM operation to the DVM target based on the DVM target being turned off.

Hardware managed power collapse and clock wake-up for memory management units and distributed virtual memory networks

Generally, aspects of this disclosure are directed to copy protection techniques. Areas in memory may be secured to establish a secure memory area in the memory that is not accessible by unauthorized clients. A request to decode video content stored in the secure memory area may be received. If the video content to be decoded is stored in the secure memory area, a first MMU associated with the hardware decoder may enforce a rule that the video content is to be decoded into one or more output buffers in the secure memory area. A request to display the decoded video content stored in the secure memory area may be received. If the decoded video content is stored in the secure memory area, a second MMU associated with a hardware display processor may enforce a rule that a secure link be established between the hardware display processor and an output device.

Hardware enforced output security settings

An interleaver that implements the LCS turbo interleaver algorithm utilized by the CDMA2000 standard is described. The interleaver includes a first computation unit for receiving an input address and computing a first sequential interleaved address during a first clock cycle in response thereto. A second computation unit is included for receiving an input address and computing a second sequential interleaved address during the first clock cycle in response thereto. The interleaver further includes a comparator for determining whether the first or the second sequential interleaved address is invalid and generating a signal in response thereto. The output of the comparator provides a control signal to a switch which selects the first or the second sequential interleaved address as an output interleaved address for the first clock cycle. The interleaver is further designed to move in a forward direction or a reverse direction.

Random-access multi-directional CDMA2000 turbo code interleaver

Techniques for polling fingers on a channel (which are fingers for which symbols are to be combined) to determine the last finger on the channel. As each finger is polled, the polled finger compares its state information with the state information for the channel to determine whether or not it is the last finger on the channel. The polled finger may be deemed as the last finger if (1) the polled finger is the current last finger, (2) the polled finger is later than the current last finger, or (3) all fingers on the channel have been polled and none of the fingers indicated that it is the last finger. If the polled finger is deemed as the last finger then, (1) the channel state information is updated with the polled finger state information, and (2) the symbols provided by the polled finger may be marked as being ready for subsequent processing.

Last finger polling for rake receivers

The present invention is a novel and improved technique for performing coding with particular application to turbo, or iterative, coding techniques. In accordance with one embodiment of the invention, interleaving is performed by generating the address of a memory using a PN state generator. Data is written into a memory in sequential order, and then read out using addresses specified by the PN state generator. To deinterleave, the interleaved data is written into a memory using addresses specified by the PN state generator, and then read out in sequential order. A set of PN state generators that provide excellent coding performance is provided.

Highly parallel map decoder

A counter for synthesizing clock signals with minimal jitter. The inventive counter has a first counter stage; a look-ahead circuit input connected to said first counter stage; and a selection circuit for choosing between an output of said first counter stage and an output of said look-ahead circuit as an output of said counter. In the specific embodiment, the first counter stage is adapted to receive a first clock signal having a frequency of N cycles per second and output a second clock signal having a frequency of M cycles per second. The first counter stage includes an accumulator having a rollover point at which an instantaneous count thereof exceeds the value of N&minus;M. The look-ahead circuit determines for a present clock cycle the rollover point for a preceding clock cycle. The look-ahead circuit is a second counter stage adapted to ascertain whether the rising edge or the trailing edge of the second clock signal is closer to the rollover point and output an indication with respect thereto.

Dual-edge M/N:D counter

The present invention is a novel and improved technique for decoding technique with particular application to turbo, or iterative, coding techniques. In accordance with one embodiment of the invention, a system for decoding includes a channel deinterleaver RAM for storing a block of symbol estimates, a set of S state metric calculators. Each state metric calculator is for generating a set of state metric calculations and a set of S&plus;1 window RAMs, wherein, S of said S&plus;1 window RAMs provide symbol estimates to said S state metric calculators. A remaining window RAM receives symbol estimates from said channel deinterleaver RAM.

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San Diego, CA, United States of America

Steven Halter