Cadence Design Systems, Inc.

Steven Guy Esposito

Jonathan Lee DeKock

Meir Ovadia

Manu Chopra

Saran Prasad

Dan Richard Kaiser

D Scott Baeder

Vincent Di Lello

Kiran Chhabra

The present disclosure relates to a computer-implemented method for use in an electronic circuit design. Embodiments may include providing an electronic design having a plurality of geometric elements and generating a non-design element. Embodiments may further include associating the non-design element with one of the plurality of geometric elements and storing the non-design element with the one of the plurality of geometric elements. Embodiments may also include displaying, at a graphical user interface, the non-design element upon selection of the geometric element.

System and method for generating non-design manipulation elements in an electronic design

The present disclosure relates to systems and methods for performing out of order name resolution in an electronic design language. Embodiments may include receiving, one or more design units associated with an electronic design and registering the one or more design units in a registry database. Embodiments may further include performing local name resolution for each element reference within at least one of the one or more design units. In response to registering, embodiments include identifying at least one element reference upon which local name resolution was not performed and obtaining an appropriate element reference from the registry database. Embodiments may further include reviewing at least one secondary design unit for one or more local declarations and performing local name resolution for one or more remaining element references using a design hierarchy.

System and method for performing out of order name resolution in an electronic design

The present disclosure relates to defining and processing hardware description language (HDL) groups. Embodiments may include mapping, using a processor, a set of tool-specific objects into a group graph with one or more groups. Embodiments may also include generating a search order associated with each group. The search order associated with each group may be based upon the hierarchical design configuration of the group graph. Embodiments may further include identifying undefined references from within a first group within the group graph and binding defined references from within the first group to electronic circuit design components. Embodiments may include identifying the undefined references from within a second group within the group graph. The second group may be selected based upon the undefined references and the search order associated with the first group.

System and method for hierarchical library searching

A test object can be selectively included in a test run based on predicting the behavior of the test object. In one embodiment, the present invention includes predicting how likely the test object is to produce a failure in a test run and deciding whether to include the test object in the test run based on the predicted likelihood. This likelihood of producing a failure may be based on any number of circumstances. For example, these circumstances may include the history of prior failures and/or the length of time since the test object was last included in a test run.

Growing community of inventors

Westford, MA, United States of America

Steven Guy Esposito