International Business Machines Corporation

Steven George Aden

Dennis G Abraham

Todd Weston Arnold

William S Rohland

Steven W Neckyfarow

Raymond Michael Higgs

Howard M Haynie

Clinton E Bubb

Michael Grassi

Luke M Hopkins

Kirk D Pospesel

Gabriel Martel Tarr

Ramanathan Raghavan

Kai Cheng

Jin Chin Wang

A system for managing one or more queues in a multi-processor environment includes a queue manager disposed in communication with a plurality of processors and a memory shared by the plurality of processors, and a queue configured to be controlled by the queue manager, the queue including independent and discrete queue elements and having a starting location specified by a base address, the queue manager having one or more dynamically configurable parameters, the one or more dynamically configurable parameters including a size of each of the queue elements. The queue manager is configured to perform receiving a message from a processor of the plurality of processors, the message including an operation address specifying a fixed storage location in the memory and a request related to accessing the memory, selecting the queue based on the operation address, and performing a queuing operation on the queue based on the request.

Configurable hardware queue management

In a first aspect, a first method of creating a programmable link delay during cycle simulation of a system is provided. The first method includes the steps of (1) modeling a system for cycle simulation, wherein the system includes (a) a plurality of links; (b) link transmitting logic adapted to transmit data on the plurality of links; (c) link receiving logic adapted to receive data from the plurality of links; and (d) link training logic coupled to the link receiving logic and adapted to compensate for skew between links; and (2) employing delay logic, coupled to the plurality of links, in the modeled system to create a known skew between links during cycle simulation. Numerous other aspects are provided.

Methods and apparatus for creating a programmable link delay

A method and system for processing multiple requests for data residing at the same memory address. The multiple requests are associated with an individual duplicate bit flag that indicates whether the request can be processed. Thus, manipulation of the duplicate bit flag controls the order of processing for each of the received requests, thereby maintaining data coherency and integrity.

Method and system for processing multiple requests for data residing at

The microprocessor resides along with its protected real address space in a secure module surrounded by tamper resistant circuitry pad. Encryption programs and encryption keys are stored in the protected memory. A second real address space is also connected to the address and data bus of the microprocessor in order to provide program and data space for a user. Gating circuitry prevent the exposure of instructions and data form the privileged memory from appearing outside of the secure module. The gating circuits switch address spaces by recognizing a sequence of predetermined addresses.

Secure computer system having privileged and unprivileged memories

An improved security system is disclosed which uses an IC card to enhance the security functions involving component authentication, user verification, user authorization and access control, protection of message secrecy and integrity, management of cryptographic keys, and auditability. Both the security method and the apparatus for embodying these functions across a total system or network using a common cryptographic architecture are disclosed. Authorization to perform these functions in the various security component device nodes in the network can be distributed to the various nodes at which they will be executed in order to personalize the use of the components.

Transaction system security method and apparatus

An improved security system is disclosed which uses an IC card to enchance the security functions involving component authentication, user verification, user authorization and access control, protection of message secrecy and integrity, management of cryptographic keys, and auditablity. Both the security method and the apparatus for embodying these functions across a total system or network using a common cryptographic architecture are disclosed. Authorization to perform there functions in the various security component device nodes in the network can be distributed to the various nodes at which they will be executed in order to personalize the use of the components.

Growing community of inventors

Cedar Park, TX, United States of America

Steven George Aden