Intel Corporation

Steven G Seidel

Stefan Rusu

Gary Leonard Woods

Travis M Eiles

Dean J Grannes

A method is provided for manufacturing a die. A supply voltage is provided to a power plane of a selected integrated circuit, formed in and on a semiconductor substrate, having a selected design, so that a respective test current flows through a plurality of test elements, of the selected integrated circuit, each being connected to a respective test point on the power plane, the test points being spaced from one another. A magnitude of each respective test current is detected. A respective test voltage is calculated at each respective test point utilizing the respective magnitude of the respective test current flowing through the respective test element connected to a respective test point. The respective test voltages are utilized to determine at which ones of the test points the respective test voltages are more than a predetermined maximum below a supply voltage. The electric design is altered to an altered electric design if any of the test voltages are below a predetermined minimum below the supply voltage. An integrated circuit having the altered design is then manufactured on another semiconductor substrate.

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Fremont, CA, United States of America

Steven G Seidel