Bae Systems Information and Electronic Systems Integration Inc.

Steven G Santee

Joseph R Marshall, Jr

Charles A Dennis

Alan F Dennis

Dale A Rickard

Robert T Carlson

Martin F Ryba

Jane O Gilliam

Forrest C Vatter

A core suitable for inclusion in an ASIC or other integrated circuit includes a plurality of SPI masters, each of which is able to control and coordinate the timing of a plurality of SPI-controlled devices via an associated SPI bus. Each SPI master is controlled by a corresponding core controller that includes memory, interrupts, flags, timers, and an instruction processor that can independently execute instructions stored in the memory to control data communication between the core controller and its associated SPI master, and between the SPI master and one or more SPI slave devices. The core controllers can be simultaneously started, resynchronized, staggered, and otherwise coordinated with each other. Embodiments further permit bypassing of the core controllers for direct data exchange between external resources and the SPI masters.

Core for controlling multiple serial peripheral interfaces (SPI's)

A flexible TOF processing block having power measurement circuitry comprising separate modules that can be modified using parameterizable registers, without complete reconstruction, allows development to continue while the overall design is optimized.

Flexible design for a tunable optical filter (TOF) processing block

A reconfigurable digital processing system for space includes the utilization of field programmable gate arrays utilizing a hardware centric approach to reconfigure software processors in a space vehicle through the reprogramming of multiple FPGAs such that one obtains a power/performance characteristic for signal processing tasks that cannot be achieved simply through the use of off-the-shelf processors. In one embodiment, for damaged or otherwise inoperable signal processors located on a spacecraft, the remaining processors which are undamaged can be reconfigured through changing the machine language and binary to the field programmable gate arrays to change the core processor while at the same time maintaining undamaged components so that the signal processing functions can be restored utilizing a RAM-based FPGA as a signal processor. In one embodiment, multiple FPGAs are connected together by a data bus and are also provided with data pipes which interconnect selected FPGAs together to provide the necessary processing function. Flexibility in reconfiguration includes the utilizing of a timing and synchronization block as well as a common configuration block which when coupled to an interconnect block permits reconfiguration of a customizable application core, depending on the particular signal processing function desired. The result is that damaged or inoperable signal processing components can be repaired in space without having to physically attend to the hardware by transmitting to the spacecraft commands which reconfigure the particular FPGAs thus to alter their signal processing function. Also mission changes can be accomplished by reprogramming the FPGAs.

Reconfigurable digital processing system for space

Growing community of inventors

Bristow, VA, United States of America

Steven G Santee