Other

Itt Corporation

Alcatel USA

International Telephone and Telegraph Corporation

Transwitch Corporation

Oxford Computer, Inc.

Steven G Morton

Enrique J Abreu

A small, rugged, concentric square, forward-pivot, assembly with motorized pan and tilt, two-point suspension of pan and tilt axes, multiple photo-sensors, and capable of using lenses that are much larger than pinhole lenses, is provided. It is combined with a motorized zoom lens, image sensor, processor and enclosure to form a covert outdoor video surveillance camera. It enables a viewing window for the lens to be small yet provide large angles of view without needing a light-losing, dark material or sharpness-losing perforated media to conceal it, and captures much more light than a pinhole. Three photo sensors are arranged around the lens and collectively control an IR-cut filter. The sensors are integrated into the assembly to point in the same direction as the lens, and provide a good assessment of the scene brightness even when some of them have been panned or tilted out of view of the window.

Small, rugged, covert outdoor PTZ camera with concentric square, pan-tilt movement and tracking photo sensors

A method provides for greatly reducing the time required for humans and machines to review long periods of recorded surveillance video, obtain images with high spatial and temporal detail, and greatly reduce the amount of data required for review. An Internet-accessible camera continuously captures video and records it internally in one or more series of short 'normal' files. Each series of normal files has a particular resolution and frame rate. Periodically, a time-lapse video is also created within the camera, from images from a number of most-recent files in a given series of normal files. A user interface enables viewing a sequence of time-lapse videos, pausing playback, and clicking over to a normal video file it was made from, to view images with greater temporal detail, and back again. The method includes multiple resolutions of normal files and multiple series of time-lapse videos with different durations and sample rates.

Video surveillance camera system with integrated time-lapse videos with multiple levels of temporal detail

A method is described for using a surveillance system to covertly and automatically determine the presence of persons and machines that do not want to be tracked and whose identities are unknown. Video is provided by one or more surveillance cameras and recorders to assist in visually distinguishing bearers of WiFi-equipped mobile devices. A processing device covertly receives WiFi probes from mobile devices, particularly smartphones, and forms and sends messages with links for viewing relevant live and recorded video. The processing device processes WiFi information, particularly mobile device signatures known as WiFi MAC addresses, organizes and records MAC addresses and other information, analyzes patterns of previous presence of MAC addresses using a variety of parameters, adjusts its processing parameters, determines when the reception of WiFi information from particular mobile devices satisfy criteria for sending messages, and presents its analysis for review and collaboration.

Methods for determining patterns of presence and ownership of mobile devices by integrating video surveillance with smartphone WiFi monitoring

A covert surveillance system for automatically determining the presence and patterns of presence of machines and especially, persons, whose identities may be unknown, sending messages with links for viewing live video and video recorded at the times of past presences, and assisting in the identification of those persons. Video is provided by one or more surveillance cameras and recording devices to assist in visually identifying the bearer of WiFi-equipped mobile devices. A computing device receives WiFi probes from mobile devices, especially smartphones, and forms and sends users messages with the identities of the computing device and mobile device, and links to a Cloud-based, video-aware portal for viewing relevant live and recorded video. The computing device processes WiFi information as it receives it, organizes and records WiFi probes in a manner that facilitates rapid searching, and determines which mobile device signatures, aka WiFi MAC addresses, satisfy criteria for sending messages.

Methods and apparatus for determining patterns of presence and ownership of mobile devices by integrating video surveillance with smartphone WiFi monitoring

A digital data processor integrated circuit (,) includes a plurality of functionally identical first processor elements (,A) and a second processor element (,). The first processor elements are bidirectionally coupled to a first cache (,) via a crossbar switch matrix (,). The second processor element is coupled to a second cache (,). Each of the first cache and the second cache contain a two-way, set-associative cache memory that uses a least-recently-used (LRU) replacement algorithm and that operates with a use-as-fill mode to minimize a number of wait states said processor elements need experience before continuing execution after a cache-miss. An operation of each of the first processor elements and an operation of the second processor element are locked together during an execution of a single instruction read from the second cache. The instruction specifies, in a first portion that is coupled in common to each of the plurality of first processor elements, the operation of each of the plurality of first processor elements in parallel. A second portion of the instruction specifies the operation of the second processor element. Also included is a motion estimator (,) and an internal data bus coupling together a first parallel port (,A), a second parallel port (,B), a third parallel port (,C), an external memory interface (,), and a data input/output of the first cache and the second cache.

Digital signal processor containing scalar processor and a plurality of vector processors operating from a single instruction

The Parallel DSP Chip has a general purpose, reduced instruction set for parallel digital signal processing. The following pertains to the preferred embodiment. Most instruction words are 32 bits long and execute at the rate of one per clock cycle. Each instruction word is executed by a single pipelined instruction unit that controls the operation of four, 16-bit vector processors in parallel with one group of bits, and the operation of a 24-bit scalar processor with another group of bits. Thus five instructions are typically executed for every instruction word as a result of the parallel architecture. A single, linear, 16 MB, memory address space is used, simplifying program development. The storage of 8- and 16-bit operands for use by the vector processors is supported to maximize memory utilization. The Parallel DSP Chip is specifically designed to support an enhanced C compiler and has two software stack pointers, one for the vector processors and one for the scalar processor, plus an interrupt stack pointer. The Parallel DSP Chip executes a single task in parallel. Using an enhanced C compiler, simple, familiar, scalar processing programming techniques can be used, and a simple, single-task operating system can be used for software development. The basic programming concept is to define one or more arrays of four-element structures using the enhanced C compiler. One element in such a structure is provided for each of the four vector processors. The structure to be processed at any one time is selected by an address computed by the scalar processor. The same operation is applied to all of the elements of the structure by the simultaneous operation of the vector processors. To access the next structure in an array of structures, the scalar processor advances the address by the number of bytes in the structure.

DPS having a plurality of like processors controlled in parallel by an

The Parallel DSP Chip has a general purpose, reduced instruction set for parallel digital signal processing. The following pertains to the preferred embodiment. Most instruction words are 32 bits long and execute at the rate of one per clock cycle. Each instruction word is executed by a single, pipelined instruction unit that controls the operation of four, 16-bit vector processors in parallel with one group of bits, and the operation of a 24-bit scalar processor with another group of bits. Thus five instructions are typically executed for every instruction word as a result of the parallel architecture. A single, linear, 16 MB, memory address space is used, simplifying program development. The storage of 8- and 16-bit operands for use by the vector processors is supported to maximize memory utilization. The Parallel DSP Chip is specifically designed to support an enhanced C compiler and has two software stack pointers, one for the vector processors and one for the scalar processor, plus an interrupt stack pointer. The Parallel DSP Chip executes a single task in parallel. Using an enhanced C compiler, simple, familiar, scalar processing programming techniques can be used, and a simple, single-task operating system can be used for software development. The basic programming concept is to define one or more arrays of four-element structures using the enhanced C compiler. One element in such a structure is provided for each of the four vector processors. The structure to be processed at any one time is selected by an address computed by the scalar processor. The same operation is applied to all of the elements of the structure by the simultaneous operation of the vector processors. To access the next structure in an array of structures, the scalar processor advances the address by the number of bytes in the structure.

DSP having a plurality of like processors controlled in parallel by an

A new form of rotating media disk drive is described. Data storage densities of many gigabits per square inch can be obtained at low cost. Data is stored in localized regions of electric charge that are stored within a thin dielectric layer that is coated upon both sides of an electrically conductive platter, rather than in magnetic domains that are stored in thin magnetizable films that are coated upon both sides of platters. Data is stored three-dimensionally, in electric dipoles whose axes are perpendicular to the plane of the platters, rather than in magnetic dipoles that lie along the surface of a platter. Data is read and written via ungated field emitter tips rather than with transformers and magnetically sensitive elements. The read/write head is built from the read/write head chip that contains field emitter tips and other elements. This chip is an active CMOS or other circuit whose active area is parallel to one side of a platter, rather than having a single, passive write element and a single, passive read element with external control circuits and amplifiers. The read/write head chip is formed in a silicon-on-insulator (SOI) wafer, with the tips and other microelectromechanical elements being formed in the top, silicon membrane, on isolated islands or pillars, and the supporting circuitry being formed in the base silicon wafer. Each read/write head chip is attached to the end of the arm of an actuator, in a manner similar to that used in magnetic disk drives. Individual, ungated field emitter tips are electrically isolated from one another and connected to, and intimately integrated with, analog and/or digital circuitry in the read/write head chip, rather than being electrically connected to many other tips and divorced from active circuitry in their immediate vicinity that controls them, as in flat panel displays. Multiple tips can be used to increase the data rate of the disk, and to provide spares to improve the reliability of the disk.

Tera-byte disk drive

A method for manufacturing ultra high resolution images, especially transmissive images, is described that is capable of fabricating images where each pixture element (pixel) has an intrinsic gray-scale, the gray-scale has a wide dynamic range, there are no voids between pixels, fabrication is not limited by the wavelength of light, and the pixels can be so tiny that their appearance is diffraction-limited. As a result, life-size images of cytology specimens can be fabricated with sufficient spatial and shading detail to show the details of the cell nuclei, and high-density, non-volatile, optical memory devices can be made. The method applies the tools of the semiconductor and optical device fabrication industries, and places registration marks on a substrate, repetitively: (1) masks the substrate, (2) places a layer of thin film upon the masked substrate, precisely registering each mask with the registration marks on the substrate, and (3) removes the mask and removes the thin film that did not land on the substrate or upon previously deposited thin film; where: (1) the optical transmission of the thin film varies from one layer to the next and is chosen from a set of transmission values, (2) the optical transmission of a given pixel is the composite of zero, one or a few thin film layers, (3) some of the thin film layers are used to form many of the pixels and some are not, and (4) the set of thin film optical transmissions is chosen in such a fashion as to give many shades while using a small number of manufacturing steps.

Optical device bearing a pattern for representing at least one image

Ultra high resolution printing method

A programmable signal generating apparatus and method are provided such as for creating a continuous SONET signal. The apparatus preferably comprises a DRAM, a memory address register, a loop counter, an address stack, an instruction decoder, and a SONET data output interface. The DRAM stores a plurality of words at a respective plurality of memory locations. Each word is preferably comprised of three bytes of SONET data and a command byte. One or more command bytes specify a command, and a plurality of commands are decoded by the decoder to generate a plurality of program sequences. The program sequences cause the SONET data bytes which are part of the data words to be generated into continuous SONET frames. The SONET data bytes do not act as typical data operands in that they have no effect upon program operation, but are simply used to generate a SONET data stream.

SONET signal generating apparatus and method

Method and apparatus including a system of integrated ciruit devices for executing matrix operations of the form [A] operated upon by [B] equals [C], where [A], [B] and [C] are each a matrix having a plurality of elements expressed in either unsigned or in two's complement format. The system includes at least one first array of data storage means organized as (j) physical rows and (k) physical columns of bits for providing storage for one bit of each of a plurality of elements of a row vectors of the matrix [A], an individual one of the (j) rows having bits of the same binary weight. The system further includes at least one second array of data storage means organized as (m) physical rows and (n) physical columns of bits, an individual one of the (m) rows storing a same binary weight bit or each of a plurality of elements of a column vector of the matrix [B]. The system further includes a processing device for processing in a predetermined manner a specified one of the (j) rows of the first array of data storage means with a specified one of the (m) rows of the second array of data storage means for producing a plurality of (x) output bits. The system also includes logic for determining a number of the output bits having a specified logic state and logic for determining a dot product.

Convolution memory

A cellular array having a plurality of processor cells disposed on a chip and interconnected by an internal bus includes data bus couplers for bidirectionally coupling to one or more external buses. The data bus couplers selectively couple buses having multiple logic levels. The number of logic levels on the coupled buses may differ. The internal bus may comprise a plurality of parallel data lines each having two-level logic such as binary data, whereas the external buses may have four-level logic represented by four voltage levels. Each data bus coupler has two-bit A/D and D/A converters parallelly connected to selectively convert two bits of two-level logic data to multiple level data and vice versa. The data bus coupler also has a logic level selector circuit using bidirectional gates for selective operation between buses having similar or dissimilar logic levels. The data bus couplers may be associated with pins organized in a regular architecture and used in connection with bedirectional transceivers to multiplex data corresponding to a multiplicity of external buses onto the internal bus and vice versa. Using this pin architecture the data bus couplers may be dynamically configured to support a collection of two-level and four-level external buses to suit the interfacing needs of the chip.

Single instruction multiple data (SIMD) cellular array processing

In an array of processing cells arranged as a single instruction multiple data processor, each processing cell contains logic which enables the cell to determine individually whether it will perform an arithmetic or logic operation or be in an idle condition. This cell-level logic includes a control register whose contents determine the operating or idle condition of the cell, and also includes PUSH/POP/COMPLEMENT stack mechanisms to represent multiple complex levels of conditions, and mechanisms to load the results of a cell-level test or arithmetic instruction into the control register, providing data-dependent control at the cell level.

Cellular array processor with individual cell-level data-dependent cell

In a cellular array including a matrixed array of processing elements, the processing elements are controlled by software to overcome manufacturing defects, to cooperate together to form words of varying size and to replace cells that become defective during the lifetime of the processor. These cells communicate with memory external to the chip via a time division multiplex bus. The bus is 32-bits wide and each cell is connected to both the upper half and the lower half of the bus. Configuration bits that are loaded into a cell cause communication over the top half or the bottom half of the bus according to the significance of the bits placed in the cells. Words between 16-bits and 246-bits in length may be formed in a case where 20 such cells are implemented on a single chip with four of the cells being deemed to be spare parts. For simplicity, typical word sizes would be 2n.times.16 bits although in principle any multiple of 16-bits may be obtained. Each cell contains a 16-bit multiport RAM providing general purpose registers for use by the programmer as well as systems registers. The systems registers accommodate the processor status word, a multiplier quotient register, a full-function arithmetic logic unit and path logic to connect the cells together and control the flow of information through the path logic according to the instruction being executed.

Growing community of inventors

Oxford, CT, United States of America

Steven G Morton