Alcatel Lucent

Nokia of America Corporation

Steven G Driediger

Michel Rochon

Adrian Grah

John Stephan Gryba

Tony D'Addona

Simon Paul Creasy

Michel Patoine

Sandy Pearse

Dmitri Garaschenko

Dorin Oprea

Dmitri Garaschencko

Various embodiments relate to a network node and method thereof including a high stability oscillator and a holdover phase-locked loop ('PLL') wherein the holdover PLL is configured to perform a holdover function by receiving a system clock signal, disciplining the high stability oscillator using the system clock signal to generate a local reference signal, and providing the local reference signal as the system clock signal when the system clock signal becomes unavailable.

Method and apparatus for performing a holdover function on a holdover line card

Various exemplary embodiments relate to a method for controlling power consumption in a telecom system. The method includes selecting a power profile command based upon a desired power consumption and performance characteristic, translating the power profile command into at least one subcommand, and initiating at least one power reduction technique in a telecom component based upon the at least one subcommand.

System and method for reducing power consumption in telecommunication systems

Various exemplary embodiments relate to a telecommunications system. The telecommunications system may include at least one actively operating component and at least one redundant component. The redundant component may include a first subcircuitry for receiving synchronization information and at least one second subcircuitry. The first subcircuitry may be activated independently of the second subcircuitry.

System and method for power reduction in redundant components

A method and apparatus for handling, maintaining, and controlling network synchronization information emanating from a plurality of line card circuits is described. The technique described may be applied to a redundant pair of line card circuits, where one line card circuit is active, while the other is inactive. Line card activity latches are managed by means of hardware logic that may be configured at the time of line card commissioning. The activity latches are coupled to a logic element. An incoming clock signal is applied to the logic element. If an activity latch indicates that a line card circuit is active, the logic element provides the incoming clock signal as an outgoing clock signal to a control card circuit. If the activity latch indicates that the line card circuit is inactive, the logic element blocks the incoming clock signal from being passed and provides a static output level as the outgoing clock signal to the control card circuit. The control card circuit is provided with circuitry to receive the outgoing clock signals from multiple line card circuits. The circuitry is sensitive to whether or not the line card circuits are configured for redundant operation. One or more of these clock signals are then selected and used for network synchronization.

Control card circuit and method for selecting a synchronization source among a plurality of line card circuits

The present invention is a specially designed PCB that allows XFP compliant transceiver modules and EMI gaskets to be used in a manner specified in the XFP standard and results in an integrated solution that is compliant with the XFP standard. Various geometric features are incorporated into the PCB to achieve improvements that in combination result in an integrated solution meeting the XFP standard. Some of these improved features include: specific thickness of prepreg and other layering of the PCB, specific spacing, dimensions and weights for certain components of the PCB, an opening on the first layer XFP cage ground shield connecting to the EMI gasket, guard ground traces in the second layer surrounding the differential pair signal traces, openings in the copper of the third layer beneath the XFP cage ground shield and XFP connector pads, and ground vias at the XFP connector and PHY connector pads.

10G XFP compliant PCB

Method and apparatus for controlling a clock signal of a line card circuit

One embodiment of the disclosures made herein is a method of detecting a transmission unit fault condition in a network system. In accordance with such a method, an operation is performed for designating transmission units received at a first counting location of a datapath, during a first duration consisting of a first specified counting interval and a first specified settling interval after the first specified counting interval elapses, as first designated transmission units. An operation is performed for determining a first datapath ingress transmission unit count for the first designated transmission units at a first counting location during the first duration. An operation is performed for determining a first datapath ingress transmission unit count, an operation is performed for determining a first datapath egress transmission unit count for the first designated transmission units at a second counting location of the datapath during the first duration. After determining the first datapath ingress transmission unit count and the first datapath egress transmission unit count, an operation is performed for indicating a transmission unit fault condition associated with the first specified counting interval when a difference is determined between the first datapath ingress transmission unit count and the first datapath egress transmission unit count after the first specified settling interval elapses.

Method and apparatus for detection of transmission unit loss and/or replication

One embodiment of the disclosures made herein is an apparatus adapted to facilitate error detection for Content Addressable Memory (CAM) modules. The apparatus includes an input error detection module and an output error detection module. The input error detection module includes a parity word generator that generates a key-based parity word after receiving a key. The key-based parity word and the key jointly define a comparand that is provided to the CAM module. The output error detection module includes a protection word generator that generates a key-based protection word after receiving the key and memory. The output error detection module includes a comparator connected to the protection word generator and to the memory. The comparator enables the predetermined protection word to be compared with the key-based protection word for facilitating issuance of an output error indication when the predetermined protection word is different than the key-based protection word.

Growing community of inventors

Ottawa, Canada

Steven G Driediger