International Business Machines Corporation

Other

Globalfoundries Inc.

Globalfoundries U.S. 2 LLC

Steven Frederick Oakland

Michael Richard Ouellette

David E Lackey

Pamela Sue Gillis

Gary Douglas Grise

Steven Michael Douskey

Darren Lane Anand

Donald Lawrence Wheater

Rudolf Adriaan Haring

Paul Gregory Crumley

Roger Paul Gregor

Arthur A Bright

Scott A Strissel

Marc B Dombrowa

Philip S Stevens

John Edward Barth, Jr

Anthony D Polson

David Brian Stone

Douglas Willard Stout

Janak G Patel

Mark C H Lamorey

Peter Slota, Jr

Vikram Iyengar

Ravi Kumar Kolagotla

Thomas Gregory Sopchak

Luke D Lacroix

Peter Verwegen

Kenneth J Shaw

Peter O Jakobsen

Jeanne Trinko-Mechler

Chris Joseph Rebeor

Bruce Cowan

David D Litten

Kerry Paul Pfarr

Maria Noack

Dennis A Miller

William R Tonti

Sebastian Theodore Ventrone

John Atkinson Fifield

David James Hathaway

Frank David Ferraiolo

Clarence Rosser Ogilvie

Paul Steven Zuchowski

Kevin William Gorman

Anne Elizabeth Gattiker

Ilya I Novof

Krishnendu Mondal

Douglas Wayne Kemerer

Leah M P Pastel

Roland A Bechade

Robert L Barry

Patrick Edward Perry

Steven Michael Eustis

Jeffery Howard Oppold

Terry Cain Coughlin, Jr

John E Andersen

Gary Stephen Ditlow

Toshiharu Saitoh

Carl Frederick Barnhart

Phil Nigh

Charles K Erdelyi

Kenneth S Gray

Richard J Grupp

Leon Skarshinski

Dac C Pham

Steven Joseph Urish

Jody John VanHorn

Michael Richard Quellette

Henry R Farmer

Bijit T Patel

John D Chickanosky

Wayne J DeGuise

Bruce Kaufmann

Anthony S Polson

James A Monzel

Gary L Kunselman

L Owen Farnsworth, Iii

Detection circuits, methods of use and manufacture and design structures are provided herein. The structure includes at least one signal line traversing one or more metal layers of an integrated circuit. Circuitry is coupled to the at least one signal line, which is structured to receive a signal with a known signal from the at least one signal line or a signal from a different potential and, based on which signal is received, determine whether there is a structural defect in the integrated circuit.

Circuit for detecting structural defects in an integrated circuit chip, methods of use and manufacture and design structures

Structures, methods, and systems for designing and verifying integrated circuits including redundant logic blocks are provided. An integrated circuit includes selection logic and selectable logic blocks that are individually controllable by the selection logic. The selectable logic blocks include respective instances of a redundant logic block, and respective instances of an interface logic block that selectively disable the redundant logic blocks in the integrated circuit.

Verifying partial good voltage island structures

A scannable register array structure includes a plurality of individual latches, each configured to hold one bit of array data in a normal mode of operation. The plurality of individual latches operate in scannable latch pairs in a test mode of operation, with first latches of the scannable latch pairs comprising L1 latches and second latches of the scannable latch pairs comprising L2 latches. A test clock signal generates a first clock pulse signal, A, for the L1 latches and a second clock pulse signal, B, for the L2 latches. The L2 latches are further configured to selectively receive L1 data therein upon a separate activation of the B clock signal, independent of the test clock signal, such that a scan out operation of the individual latches results in observation of L1 latch data.

Dense register array for enabling scan out observation of both L1 and L2 latches

Built-in self-test (BIST) microcontroller integrated circuit adapted for logic verification. Microcontroller includes a plurality of hardware description language files representing a hierarchical description of the microcontroller, the plurality of hardware description language files including a library of circuit design elements, a plurality of library design circuit elements adapted to store a uniquely defined set of input and output signals to enable a logic BIST, and a plurality of latches adapted to store a plurality of values corresponding to a behavioral profile of a test clock.

Microcontroller for logic built-in self test (LBIST)

A system and method for detecting hold path faults in an integrated circuit is provided in exemplary embodiments. These exemplary embodiments introduce a method of identifying data paths within an integrated circuit with statistically the highest timing slack among the data paths within the integrated circuit that cover the entire process space of the circuit. By identifying these paths (i.e., shortest data paths), a robust test pattern can be generated that directly tests for hold path faults on short data paths within the integrated circuit using one functional clock pulse.

Method to test hold path faults using functional clocking

A method of hold fault modeling and test generation. The method includes first modeling a fast-to-rise and a fast-to-fall hold fault for a plurality of circuit nets. Testing a fast-to-rise hold fault is accomplished by: setting up a logic value on each of the plurality of circuit nodes to 0; transitioning each of the plurality of circuit nodes from 0 to 1 with a single clock pulse; and determining if at least one downstream node was inadvertently impacted by the transitioning from 0 to 1. Testing a fast-to-fall hold is accomplished by: setting up a logic value on each of the plurality circuit nodes to 1; transitioning each of the plurality of circuit nodes from 1 to 0 with a single clock pulse; and determining if at least one downstream node was inadvertently impacted by the transitioning from 1 to 0.

Hold transition fault model and test generation method

A method and circuits for testing an integrated circuit at functional clock frequency by providing a test controller generating control signals that assure proper latching of test patterns in scan chains at tester frequency and propagation of the test pattern through logic circuits being tested at functional clock frequency.

Functional frequency testing of integrated circuits

A system and methods of balancing scan chains and, more particularly, a system and methods of load balancing scan chains into hierarchically designed integrated circuits. The method includes estimating or calculating a maximum scan chain length L and creating a maximum number of scan chains of length L in each hierarchical block. The method further includes distributing remaining scan bits in each hierarchical block into additional scan chains, and creating chip-level scan chains by using the scan chains of maximum length L and by forming additional chip-level scan chains of maximum length L by distributing the additional scan chains of maximum length LR, plus any remaining top-level scan bits, among the additional chip-level scan chains of maximum length L.

System and methods of balancing scan chains and inserting the balanced-length scan chains into hierarchically designed integrated circuits

An edge triggered system is provided having a data and scan input includes a latch device having a clock input and an AND gate, coupled to the latch device, structured and arranged to receive a first clock signal and an inverted clock signal to generate a clock to the clock input. A process for operating an edge triggered system having a data and scan input includes forwarding a first clock signal to an input of an AND gate. The method includes inverting a second clock signal forwarded to another input of the AND gate and generating a clock input for a latch device from the AND gate.

Latch and clock structures for enabling race-reduced MUX scan and LSSD co-compatibility

Latch and clock structures for enabling race-reduced mux scan and LSSD co-compatibility

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Colchester, VT, United States of America

Steven Frederick Oakland