Sun Microsystems, Inc.

Oracle America, Inc.

Steven Fitzgerald Weiss

Andrew E Phelps

Patricia Shanahan

Eric Eugene Graf

Daniel P Drogichen

Douglas B Meyer

Donald Kane

Don Kane

A method and apparatus for implementation of a pipeline structure for data transfer. A request is received from a first domain to access a second domain during a first clock cycle. A pipeline structure is used to perform at least a portion of the request during a subsequent clock cycle.

Pipeline structure for a shared memory protocol

The present invention provides a method and apparatus for design verification. The method comprises operating a device in the system in a first state, modifying at least one operational characteristic of the device to operate in a second state, and determining if an error condition occurs in the system in response to modifying the operational characteristic of the device. The apparatus comprises an interface and a verification module adapted to receive a control signal from the interface and to adjust an operating characteristic of the apparatus to exercise a system in a manner that is capable of revealing one or more error conditions in the system in response to receiving the control signal.

System design verification using selected states of a processor-based system to reveal deficiencies

A method and apparatus for providing error isolation in a multi-domain computer system. The system includes a plurality of system resources allocated to form at least a first and second domain. The system resources of the first domain perform a set of transactions independent from a set of transactions performed by the system resources of the second domain. The system further comprises at least one interface for coupling one system resource from the first domain and one system resource from the second domain. The at least one interface tracks the set of transactions performed by the one system resource of the first domain and the one system resource of the second domain independently from one another.

Method and apparatus for providing error isolation in a multi-domain computer system

A multiprocessing computer system provides the hardware support to properly test an I/O board while the system is running user application programs and while preventing a faulty board from causing a system crash. The system includes a centerplane that mounts multiple expander boards. Each expander board in turn connects a microprocessor board and an I/O board to the centerplane. Prior to testing, the replacement I/O board becomes a part of a dynamic system domain software partition after it has been inserted into an expander board of the multiprocessing computer system. Testing an I/O board involves executing a process using a microprocessor and memory on a microprocessor board to perform hardware tests on the I/O board. An error cage, address transaction cage, and interrupt transaction cage isolate any errors generated while the I/O board is being tested. The error cage isolates correction code errors, parity errors, protocol errors, timeout errors, and other similar errors generated by the I/O board under test. The address transaction cage isolates out of range memory addresses from the I/O board under test. The interrupt transaction cage isolates interrupt requests to an incorrect target port generated by the I/O board under test. The errors generated by the I/O board are logged in a status register and suppressed.

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San Diego, CA, United States of America

Steven Fitzgerald Weiss